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/linux/Documentation/devicetree/bindings/iommu/
H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
10 - Konrad Dybcio <konradybcio@kernel.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
[all …]
H A Dqcom,apq8064-iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm APQ8064 IOMMU
11 - David Heidelberg <david@ixit.cz>
14 The MSM IOMMU is an implementation compatible with the ARM VMSA short
16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
20 const: qcom,apq8064-iommu
24 - description: interface clock for register accesses
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H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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H A Drenesas,ipmmu-vmsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas VMSA-Compatible IOMMU
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
15 connected to the IPMMU through a port called micro-TLB.
20 - items:
21 - enum:
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/linux/drivers/iommu/arm/arm-smmu/
H A Dqcom_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-mapping.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
33 #include "arm-smmu.h"
47 /* IOMMU core code handle */
48 struct iommu_device iommu; member
69 struct mutex init_mutex; /* Protects iommu pointer */
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H A Darm-smmu-qcom-debug.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include "arm-smmu.h"
20 #include "arm-smmu-qcom.h"
74 dev_err(smmu->dev, "TLB sync timed out -- SMMU may be deadlocked\n"); in qcom_smmu_tlb_sync_debug()
76 cfg = qsmmu->data->cfg; in qcom_smmu_tlb_sync_debug()
80 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_TBU_PWR_STATUS], in qcom_smmu_tlb_sync_debug()
83 dev_err(smmu->dev, in qcom_smmu_tlb_sync_debug()
86 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_STATS_SYNC_INV_TBU_ACK], in qcom_smmu_tlb_sync_debug()
89 dev_err(smmu->dev, in qcom_smmu_tlb_sync_debug()
92 ret = qcom_scm_io_readl(smmu->ioaddr + cfg->reg_offset[QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR], in qcom_smmu_tlb_sync_debug()
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H A Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for ARM architected SMMU implementations.
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-mapping.h>
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/linux/Documentation/admin-guide/
H A Dthunderbolt.rst1 .. SPDX-License-Identifier: GPL-2.0
22 is expected to be accompanied with an IOMMU based DMA protection.
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in Documentation/ABI/testing/sysfs-bus-thunderbolt.
35 ``/etc/udev/rules.d/99-local.rules``::
47 knowing about it. There are ways to prevent this by setting up an IOMMU but
64 In BIOS settings this is typically called *Unique ID*.
66 secure
68 addition to UUID the device (if it supports secure connect) is sent
[all …]
/linux/drivers/iommu/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
13 #include <linux/io-pgtable.h>
18 #include <linux/iommu.h>
25 #include "msm_iommu_hw-8xxx.h"
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
[all …]
H A Dmtk_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
6 #include <linux/arm-smccc.h>
15 #include <linux/iommu.h>
17 #include <linux/io-pgtable.h>
36 #include <dt-bindings/memory/mtk-memory-port.h>
113 /* Macro for 5 bits length port ID field (default) */
116 /* Macro for 6 bits length port ID field */
138 #define STD_AXI_MODE BIT(12) /* For non MM iommu */
139 /* 2 bits: iommu type */
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/linux/Documentation/driver-api/
H A Dvfio-mediated-device.rst1 .. SPDX-License-Identifier: GPL-2.0-only
17 The number of use cases for virtualizing DMA devices that do not have built-in
25 an IOMMU/device-agnostic framework for exposing direct device access to user
26 space in a secure, IOMMU-protected environment. This framework is used for
37 * Add a mediated device to and remove it from an IOMMU group
44 The following high-level block diagram shows the main components and interfaces
48 +---------------+
50 | +-----------+ | mdev_register_driver() +--------------+
51 | | | +<------------------------+ |
53 | | bus | +------------------------>+ vfio_mdev.ko |<-> VFIO user
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/linux/Documentation/arch/x86/
H A Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
22 Use of SVA requires IOMMU support in the platform. IOMMU is also
24 to cache translations for virtual addresses. The IOMMU driver uses the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
53 record, and the PASID (process address space ID) of the current process.
55 ENQCMD works with non-posted semantics and carries a status back if the
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
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/linux/Documentation/arch/s390/
H A Dvfio-ap.rst13 The AP adapter cards are exposed via the AP bus. The motivation for vfio-ap
45 sub-directory::
57 domain can be configured with a secure private key used for clear key
65 usage domain; for example, to set the secure private key for the control
76 significant bit, correspond to domains 0-255.
82 comprised of an AP adapter ID (APID) and an AP queue index (APQI). The
111 * NQAP: to enqueue an AP command-request message to a queue
112 * DQAP: to dequeue an AP command-reply message from a queue
132 an APID from 0-255. If a bit is set, the corresponding adapter is valid for
137 corresponds to an AP queue index (APQI) from 0-255. If a bit is set, the
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-thunderbolt29 de-authorization of devices. Value of 1 means user can
30 de-authorize PCIe tunnel by writing 0 to authorized
37 Description: This attribute tells whether the system uses IOMMU
38 for DMA protection. Value of 1 means IOMMU is used 0 means
53 secure Require devices that support secure connect at
78 0 The device will be de-authorized (only supported if
87 0 The device will be de-authorized (only supported if
117 Description: When a devices supports Thunderbolt secure connect it will
119 authorization to use the secure connection method instead.
127 Description: This attribute contains id of this device extracted from
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/linux/arch/arm/mach-omap2/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
7 obj-y := id.o io.o control.o devices.o fb.o pm.o \
8 common.o dma.o omap-headsmp.o sram.o
10 hwmod-common = omap_hwmod.o \
15 clock-common = clock.o
16 secure-common = omap-smc.o omap-secure.o
18 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
19 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
20 obj-$(CONFIG_ARCH_OMAP4) += $(secure-common)
21 obj-$(CONFIG_SOC_AM33XX) += $(secure-common)
[all …]
H A Dpdata-quirks.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <linux/platform_data/pinctrl-single.h>
21 #include <linux/platform_data/hsmmc-omap.h>
22 #include <linux/platform_data/iommu-omap.h>
23 #include <linux/platform_data/ti-sysc.h>
25 #include <linux/platform_data/asoc-ti-mcbsp.h>
26 #include <linux/platform_data/ti-prm.h>
30 #include "common-board-devices.h"
33 #include "omap-secure.h"
58 * Note that if the pins are used for MMC1, pbias-regulator
[all …]
/linux/drivers/iommu/iommufd/
H A Ddriver.c1 // SPDX-License-Identifier: GPL-2.0-only
6 /* Driver should use a per-structure helper in include/linux/iommufd.h */
12 return -EINVAL; in _iommufd_object_depend()
14 if (obj_dependent->type != obj_depended->type) in _iommufd_object_depend()
15 return -EINVAL; in _iommufd_object_depend()
17 refcount_inc(&obj_depended->users); in _iommufd_object_depend()
22 /* Driver should use a per-structure helper in include/linux/iommufd.h */
27 obj_dependent->type != obj_depended->type)) in _iommufd_object_undepend()
30 refcount_dec(&obj_depended->users); in _iommufd_object_undepend()
37 * Driver should use a per-structure helper in include/linux/iommufd.h
[all …]
H A Ddevice.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES
4 #include <linux/iommu.h>
6 #include <linux/pci-ats.h>
10 #include "../iommu-priv.h"
31 WARN_ON(!xa_empty(&igroup->pasid_attach)); in iommufd_group_release()
33 xa_cmpxchg(&igroup->ictx->groups, iommu_group_id(igroup->group), igroup, in iommufd_group_release()
35 iommu_group_put(igroup->group); in iommufd_group_release()
36 mutex_destroy(&igroup->lock); in iommufd_group_release()
42 kref_put(&group->ref, iommufd_group_release); in iommufd_put_group()
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/linux/include/uapi/linux/
H A Diommufd.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* Copyright (c) 2021-2022, NVIDIA CORPORATION & AFFILIATES.
23 * - ENOTTY: The IOCTL number itself is not supported at all
24 * - E2BIG: The IOCTL number is supported, but the provided structure has
25 * non-zero in a part the kernel does not understand.
26 * - EOPNOTSUPP: The IOCTL number is supported, and the structure is
29 * - EINVAL: Everything about the IOCTL was understood, but a field is not
31 * - ENOENT: An ID or IOVA provided does not exist.
32 * - ENOMEM: Out of memory.
33 * - EOVERFLOW: Mathematics overflowed.
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
18 interrupt-parent = <&intc>;
[all …]
H A Dmsm8917.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
8 #include <dt-bindings/thermal/thermal.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
[all …]
/linux/drivers/gpu/host1x/
H A Ddev.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2012-2015, NVIDIA Corporation.
10 #include <linux/iommu.h>
34 unsigned int id);
80 struct host1x *host, unsigned int id, u32 thresh);
81 void (*enable_syncpt_intr)(struct host1x *host, unsigned int id);
82 void (*disable_syncpt_intr)(struct host1x *host, unsigned int id);
116 * On T20-T148, the boot chain may setup DC to increment syncpoints
122 * On Tegra186, secure world applications may require access to
191 host->syncpt_op->restore(sp); in host1x_hw_syncpt_restore()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
/linux/drivers/memory/tegra/
H A Dtegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017-2025 NVIDIA CORPORATION. All rights reserved.
7 #include <linux/iommu.h>
17 #include <dt-bindings/memory/tegra186-mc.h>
28 struct platform_device *pdev = to_platform_device(mc->dev); in tegra186_mc_probe()
43 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast"); in tegra186_mc_probe()
45 mc->bcast_ch_regs = mc->regs; in tegra186_mc_probe()
47 if (IS_ERR(mc->bcast_ch_regs)) { in tegra186_mc_probe()
48 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) { in tegra186_mc_probe()
49 dev_warn(&pdev->dev, in tegra186_mc_probe()
[all …]
/linux/include/acpi/
H A Dactbl2.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
4 * Name: actbl2.h - ACPI Table Definitions
6 * Copyright (C) 2000 - 2025, Intel Corp.
54 #define ACPI_SIG_RHCT "RHCT" /* RISC-V Hart Capabilities Table */
55 #define ACPI_SIG_RIMT "RIMT" /* RISC-V IO Mapping Table */
58 #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */
64 * All tables must be byte-packed to match the ACPI specification, since
74 * essentially useless for dealing with packed data in on-disk formats or
83 * AEST - Arm Error Source Table
94 /* Common Subtable header - one per Node Structure (Subtable) */
[all …]

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