| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_tlb_inval.c | 20 * DOC: Xe TLB invalidation
22 * Xe TLB invalidation is implemented in two layers. The first is the frontend
27 * interacts with the hardware (or firmware) to perform the actual invalidation.
90 "TLB invalidation fence timeout, seqno=%d recv=%d", in xe_tlb_inval_fence_timeout()
103 * tlb_inval_fini - Clean up TLB invalidation state
108 * TLB invalidation state.
128 * xe_gt_tlb_inval_init_early() - Initialize TLB invalidation state
131 * Initialize TLB invalidation state, purely software initialization, should
172 * xe_tlb_inval_reset() - TLB invalidation reset
173 * @tlb_inval: TLB invalidation client
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| H A D | xe_tlb_inval_job.c | 19 /** struct xe_tlb_inval_job - TLB invalidation job */
23 /** @tlb_inval: TLB invalidation client */
27 /** @vm: VM which TLB invalidation is being issued for */
83 * xe_tlb_inval_job_create() - TLB invalidation job create
85 * @tlb_inval: TLB invalidation client
87 * @vm: VM which TLB invalidation is being issued for
92 * Create a TLB invalidation job and initialize internal fields. The caller is
95 * Return: TLB invalidation job object on success, ERR_PTR failure
157 * @job: TLB invalidation job that may trigger reclamation
201 * xe_tlb_inval_job_alloc_dep() - TLB invalidation job alloc dependency
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| /linux/arch/arm64/include/asm/ |
| H A D | tlbflush.h | 120 * the level at which the invalidation must take place. If the level is
121 * wrong, no invalidation may take place. In the case where the level
123 * a non-hinted invalidation. Any provided level outside the hint range
124 * will also cause fall-back to non-hinted invalidation.
126 * For Stage-2 invalidation, use the level values provided to that effect
280 * TLB Invalidation
283 * This header file implements the low-level TLB invalidation routines
286 * Every invalidation operation uses the following template:
290 * DSB ISH // Ensure the TLB invalidation has completed
295 * The following functions form part of the "core" TLB invalidation API,
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| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-intel-iommu | 121 This file exports invalidation queue internals of each
130 Invalidation queue on IOMMU: dmar0
144 Invalidation queue on IOMMU: dmar1
168 * 1 - enable sampling IOTLB invalidation latency data
170 * 2 - enable sampling devTLB invalidation latency data
172 * 3 - enable sampling intr entry cache invalidation latency data
185 2) Enable sampling IOTLB invalidation latency data
207 3) Enable sampling devTLB invalidation latency data
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| /linux/drivers/gpu/drm/i915/gt/uc/abi/ |
| H A D | guc_actions_abi.h | 196 * 0: Heavy mode of Invalidation:
197 * The pipeline of the engine(s) for which the invalidation is targeted to is
199 * Observed before completing the TLB invalidation
200 * 1: Lite mode of Invalidation:
203 * completing TLB invalidation.
204 * Light Invalidation Mode is to be used only when
206 * for the in-flight transactions across the TLB invalidation. In other words,
207 * this mode can be used when the TLB invalidation is intended to clear out the
208 * stale cached translations that are no longer in use. Light Invalidation Mode
209 * is much faster than the Heavy Invalidation Mode, as it does not wait for the
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| /linux/Documentation/driver-api/ |
| H A D | generic_pt.rst | 111 IOMMU Invalidation Features
114 Invalidation is how the page table algorithms synchronize with a HW cache of the
125 single range invalidation for each operation, over-invalidating if there are
126 gaps of VA that don't need invalidation. This trades off impacted VA for number
127 of invalidation operations. It does not keep track of what is being invalidated;
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| /linux/drivers/infiniband/ulp/rtrs/ |
| H A D | README | 54 The procedure is the default behaviour of the driver. This invalidation and
165 the user header, flags (specifying if memory invalidation is necessary) and the
169 attaches an invalidation message if requested and finally an "empty" rdma
176 or in case client requested invalidation:
184 the user header, flags (specifying if memory invalidation is necessary) and the
190 attaches an invalidation message if requested and finally an "empty" rdma
201 or in case client requested invalidation:
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| /linux/arch/powerpc/include/asm/ |
| H A D | pnv-ocxl.h | 19 /* Radix Invalidation Control
28 /* Invalidation Criteria
35 /* Invalidation Flag */
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| /linux/Documentation/filesystems/caching/ |
| H A D | netfs-api.rst | 36 (8) Data file invalidation
39 (11) Page release and invalidation
285 The read operation will fail with ESTALE if invalidation occurred whilst the
302 Data File Invalidation
319 This increases the invalidation counter in the cookie to cause outstanding
324 Invalidation runs asynchronously in a worker thread so that it doesn't block
427 Page Release and Invalidation
442 Page release and page invalidation should also wait for any mark left on the
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| /linux/Documentation/gpu/ |
| H A D | drm-vm-bind-locking.rst | 87 notifier invalidation. This is not a real seqlock but described in
95 invalidation notifiers.
103 invalidation. The userptr notifier lock is per gpu_vm.
406 <Invalidation example>` below). Note that when the core mm decides to
435 // invalidation notifier running anymore.
449 // of the MMU invalidation notifier. Hence the
476 The userptr gpu_vma MMU invalidation notifier might be called from
495 // invalidation callbacks, the mmu notifier core will flip
504 When this invalidation notifier returns, the GPU can no longer be
564 invalidation notifier where zapping happens. Hence, if the
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| /linux/include/linux/ |
| H A D | memregion.h | 43 * contents while performing the invalidation. It is only exported for
61 WARN_ON_ONCE("CPU cache invalidation required"); in cpu_cache_invalidate_memregion()
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| H A D | io-pgtable.h | 30 * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a
31 * single page. IOMMUs that cannot batch TLB invalidation
34 * and defer the invalidation until iommu_iotlb_sync() instead.
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| /linux/arch/powerpc/kernel/ |
| H A D | l2cr_6xx.S | 60 - L2I set to perform a global invalidation
111 /* Before we perform the global invalidation, we must disable dynamic
207 /* Perform a global invalidation */
223 /* Wait for the invalidation to complete */
342 /* Perform a global invalidation */
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | l2_cache.json | 12 …he L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line …
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gmc_v11_0.c | 259 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v11_0_flush_gpu_tlb()
260 * release after invalidation to avoid entering power gated state in gmc_v11_0_flush_gpu_tlb()
294 /* Issue additional private vm invalidation to MMHUB */ in gmc_v11_0_flush_gpu_tlb()
301 /* Issue private invalidation */ in gmc_v11_0_flush_gpu_tlb()
303 /* Read back to ensure invalidation is done*/ in gmc_v11_0_flush_gpu_tlb()
320 * @inst: is used to select which instance of KIQ to use for the invalidation
361 * off cycle, add semaphore acquire before invalidation and semaphore in gmc_v11_0_emit_flush_gpu_tlb()
362 * release after invalidation to avoid entering power gated state in gmc_v11_0_emit_flush_gpu_tlb()
390 * add semaphore release after invalidation, in gmc_v11_0_emit_flush_gpu_tlb()
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| H A D | amdgpu_hmm.c | 42 * page table invalidation are completed and we once more see a coherent process
58 * @range: details on the invalidation
97 * @range: details on the invalidation
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| H A D | gmc_v12_1.c | 330 /* Issue additional private vm invalidation to MMHUB */ in gmc_v12_1_flush_vm_hub()
337 /* Issue private invalidation */ in gmc_v12_1_flush_vm_hub()
339 /* Read back to ensure invalidation is done*/ in gmc_v12_1_flush_vm_hub()
403 * @inst: is used to select which instance of KIQ to use for the invalidation
492 * add semaphore release after invalidation, in gmc_v12_1_emit_flush_gpu_tlb()
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | l2_cache.json | 12 …he L2 (from other CPUs) which return data even if the snoops cause an invalidation. L2 cache line …
44 …"PublicDescription": "Counts each explicit invalidation of a cache line in the level 2 cache by ca…
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| /linux/drivers/cxl/ |
| H A D | Kconfig | 222 to invalidate caches when those events occur. If that invalidation
224 invalidation failure are due to the CPU not providing a cache
225 invalidation mechanism. For example usage of wbinvd is restricted to
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| /linux/drivers/iommu/arm/arm-smmu-v3/ |
| H A D | arm-smmu-v3.h | 753 * struct arm_smmu_invs - Per-domain invalidation array
763 * @inv: flexible invalidation array
775 * Concurrent invalidation thread will push every invalidation described in the
776 * array into the command queue for each invalidation event. It is designed like
777 * this to optimize the invalidation fast path by avoiding locks.
782 * concurrent invalidation thread accessing the old array from issuing commands
1006 * invalidation array. It'll be pre-allocated with enough enries for all
1138 /* No concurrency with invalidation is possible at this point */ in arm_smmu_domain_free()
1182 * struct arm_smmu_inv_state - Per-domain invalidation array state
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| /linux/lib/ |
| H A D | cache_maint.c | 6 * iterate over each registered instance to first kick off invalidation and
130 * Machines that do not support invalidation, e.g. VMs, will not have any
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| /linux/virt/kvm/ |
| H A D | pfncache.c | 6 * memory with suitable invalidation mechanisms.
41 * be modified, and invalidation would no longer be in gfn_to_pfn_cache_invalidate_start()
42 * necessary. Hence check again whether invalidation in gfn_to_pfn_cache_invalidate_start()
132 * be used here because the invalidation of caches in the in mmu_notifier_retry_cache()
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| /linux/drivers/media/pci/intel/ipu6/ |
| H A D | ipu6.h | 138 * MMU Invalidation HW bug workaround by ZLW mechanism
140 * Old IPU6 MMUV2 has a bug in the invalidation mechanism which might result in
142 * corruption. So we cannot directly use the MMU V2 invalidation registers
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| /linux/arch/arm64/kvm/ |
| H A D | vmid.c | 65 * flush_pending and issuing a local context invalidation on in flush_context()
67 * invalidation over the inner shareable domain on rollover. in flush_context()
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| /linux/Documentation/gpu/rfc/ |
| H A D | gpusvm.rst | 32 * GPU page table invalidation, which requires a GPU virtual address, is
56 change rather the driver only receiving the invalidation notifier.
|