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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
[all …]
H A Dfsl-ls2088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 /dts-v1/;
14 #include "fsl-ls2088a.dtsi"
15 #include "fsl-ls208xa-rdb.dtsi"
19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
22 stdout-path = "serial1:115200n8";
27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
[all …]
H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
33 compatible = "gpio-keys";
35 power-button {
[all …]
H A Dfsl-lx2160a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2018-2020 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a-rev2.dtsi"
13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dintegratorap-im-pd1.dts1 // SPDX-License-Identifier: GPL-2.0
4 * with the IM-PD1 example logical module mounted.
10 model = "ARM Integrator/AP with IM-PD1";
11 compatible = "arm,integrator-ap";
13 reserved-memory {
14 #address-cells = <1>;
15 #size-cells = <1>;
19 /* 1 MB of designated video RAM on the IM-PD1 */
20 compatible = "shared-dma-pool";
22 no-map;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp-pmics.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
7 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
8 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/spmi/spmi.h>
14 thermal-zones {
15 pm8280_1_thermal: pm8280-1-thermal {
16 polling-delay-passive = <100>;
[all …]
H A Dlemans-pmics.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/spmi/spmi.h>
10 thermal-zones {
11 pmm8654au_0_thermal: pm8775-0-thermal {
12 polling-delay-passive = <100>;
14 thermal-sensors = <&pmm8654au_0_temp_alarm>;
31 pmm8654au_1_thermal: pm8775-1-thermal {
32 polling-delay-passive = <100>;
34 thermal-sensors = <&pmm8654au_1_temp_alarm>;
[all …]
H A Dpm4125.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/iio/qcom,spmi-vadc.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/spmi/spmi.h>
13 compatible = "qcom,pm2250", "qcom,spmi-pmic";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "qcom,pm8916-pon";
23 compatible = "qcom,pm8941-pwrkey";
[all …]
/linux/Documentation/devicetree/bindings/counter/
H A Dinterrupt-counter.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Oleksij Rempel <o.rempel@pengutronix.de>
17 Interrupts or gpios are required. If both are defined, the interrupt will
18 take precedence for counting interrupts.
22 const: interrupt-counter
24 interrupts:
31 - compatible
[all …]
/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
34 ref_100m: clock-ref-100m {
35 compatible = "fixed-clock";
[all …]
H A Dloongson-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
35 ref_100m: clock-ref-100m {
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-corsola-squirtle.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "mt8186-corsola-voltorb.dtsi"
12 chassis-type = "convertible";
19 interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
20 pinctrl-names = "default";
21 pinctrl-0 = <&touchscreen_pins>;
22 reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
23 vcc33-supply = <&pp3300_s3>;
24 status = "fail-needs-probe";
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
[all …]
H A Dthead,c900-aclint-mtimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ACLINT Machine-level Timer Device
10 - Inochi Amaoto <inochiama@outlook.com>
15 - items:
16 - enum:
17 - sophgo,sg2042-aclint-mtimer
18 - sophgo,sg2044-aclint-mtimer
[all …]
H A Dandestech,plmt0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Andes machine-level timer
10 The Andes machine-level timer device (PLMT0) provides machine-level timer
11 functionality for a set of HARTs on a RISC-V platform. It has a single
12 fixed-frequency monotonic time counter (MTIME) register and a time compare
17 - Ben Zong-You Xie <ben717@andestech.com>
22 - enum:
23 - andestech,qilai-plmt
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dandestech,plicsw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Andes machine-level software interrupt controller
12 controller (PLIC_SW). PLIC_SW directly connects to the machine-mode
13 inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interrupt
15 generate machine-mode inter-processor interrupts through programming its
19 - Ben Zong-You Xie <ben717@andestech.com>
24 - enum:
[all …]
H A Dinterrupts.txt5 -------------------------
7 Nodes that describe devices which generate interrupts must contain an
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
13 which the interrupts are routed; see section 2 below for details.
16 interrupt-parent = <&intc1>;
17 interrupts = <5 0>, <6 0>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-39x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dpm8058.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #interrupt-cells = <2>;
7 interrupt-controller;
8 #address-cells = <1>;
9 #size-cells = <0>;
12 compatible = "qcom,pm8058-pwrkey";
14 interrupts-extended = <&pm8058 50 IRQ_TYPE_EDGE_RISING>,
17 pull-up;
21 compatible = "qcom,pm8058-keypad-led";
27 compatible = "qcom,pm8058-vib";
[all …]
/linux/arch/arm/boot/dts/st/
H A Dste-href-tvk1281618-r2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "gpio-keys";
12 #address-cells = <1>;
13 #size-cells = <0>;
14 vdd-supply = <&ab8500_ldo_aux1_reg>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
37 interrupt-parent = <&gpio6>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f0-spider-ethernet.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Spider Ethernet sub-board
23 label = "ethernet-sub-board";
33 power-source = <1800>;
39 power-source = <1800>;
45 power-source = <1800>;
50 pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
51 pinctrl-names = "default";
57 phy-handle = <&u101>;
58 phy-mode = "sgmii";
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
33 pinctrl-0 = <&usart0_pins>;
[all …]
/linux/include/linux/rtc/
H A Dds1685.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * DS1685/DS1687-series RTC chips.
8 * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
11 * Copyright (C) 2011-2014 Joshua Kinard <linux@kumba.dev>.
12 * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
15 * DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
16 * DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
17 * DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
18 * Application Note 90, Using the Multiplex Bus RTC Extended Features.
29 * struct ds1685_priv - DS1685 private data structure.
[all …]

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