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/linux/Documentation/devicetree/bindings/counter/
H A Dinterrupt-counter.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Interrupt counter
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 A generic interrupt counter to measure interrupt frequency. It was developed
17 Interrupts or gpios are required. If both are defined, the interrupt will
22 const: interrupt-counter
31 - compatible
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/linux/drivers/comedi/drivers/
H A Damplc_dio200.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
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H A Damplc_dio200_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
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H A Ddas16m1.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Comedi driver for CIO-DAS16/M1
7 * COMEDI - Linux Control and Measurement Device Interface
13 * Description: CIO-DAS16/M1
15 * Devices: [Measurement Computing] CIO-DAS16/M1 (das16m1)
18 * This driver supports a single board - the CIO-DAS16/M1. As far as I know,
20 * CIO-DAS16/M1/16 is significantly different.
23 * a hard real-time interrupt (set the TRIG_RT flag in your struct comedi_cmd
25 * pulling the data across the ISA bus. I timed the interrupt handler, and it
28 * time in the interrupt handler.
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H A Ds626.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
51 * counter channel.
73 /* Interrupt enable bit in ISR and IER. */
79 #define S626_IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */
80 #define S626_IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */
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H A Dicp_multi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1997-2002 David A. Schleef <ds@schleef.org>
23 * It has 16 single-ended or 8 differential Analogue Input channels with
24 * 12-bit resolution. Ranges : 5V, 10V, +/-5V, +/-10V, 0..20mA and 4..20mA.
28 * There are 4 x 12-bit Analogue Outputs. Ranges : 5V, 10V, +/-5V, +/-10V
34 * 4 x 16-bit counters - not implemented
59 #define ICP_MULTI_INT_EN 0x0c /* R/W: Interrupt enable register */
60 #define ICP_MULTI_INT_STAT 0x0e /* R/W: Interrupt status register */
61 #define ICP_MULTI_INT_ADC_RDY BIT(0) /* A/D conversion ready interrupt */
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/linux/drivers/counter/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Counter devices
8 select COUNTER
21 menuconfig COUNTER config
22 tristate "Counter support"
24 This enables counter device support through the Generic Counter
26 one or more of the counter device drivers below.
28 if COUNTER
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
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H A Dinterrupt-cnt.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/counter.h>
9 #include <linux/interrupt.h>
17 #define INTERRUPT_CNT_NAME "interrupt-cnt"
32 struct counter_device *counter = dev_id; in interrupt_cnt_isr() local
33 struct interrupt_cnt_priv *priv = counter_priv(counter); in interrupt_cnt_isr()
35 atomic_long_inc(&priv->count); in interrupt_cnt_isr()
37 counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); in interrupt_cnt_isr()
42 static int interrupt_cnt_enable_read(struct counter_device *counter, in interrupt_cnt_enable_read() argument
45 struct interrupt_cnt_priv *priv = counter_priv(counter); in interrupt_cnt_enable_read()
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/linux/drivers/net/wan/
H A Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
36 /* Interrupt Registers */
37 #define IVR 0x60 /* Interrupt Vector Register */
38 #define IMVR 0x64 /* Interrupt Modified Vector Register */
39 #define ITCR 0x68 /* Interrupt Control Register */
40 #define ISR0 0x6c /* Interrupt Status Register 0 */
41 #define ISR1 0x70 /* Interrupt Status Register 1 */
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/linux/arch/mips/kernel/
H A Dcevt-r4k.c7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
10 #include <linux/interrupt.h>
17 #include <asm/cevt-r4k.h>
28 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; in mips_next_event()
33 * calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
67 cnt = read_c0_count() - cnt; in calculate_min_delta()
73 j, ARRAY_SIZE(buf1) - 1); in calculate_min_delta()
74 for (; l > k; --l) in calculate_min_delta()
75 buf1[l] = buf1[l - 1]; in calculate_min_delta()
85 if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) { in calculate_min_delta()
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/linux/drivers/net/ethernet/freescale/
H A Dgianfar.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
27 #include <linux/interrupt.h>
67 #define DRV_NAME "gfar-enet"
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
108 * time described by a value of 1 in the interrupt
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/linux/drivers/net/ethernet/sun/
H A Dsunbmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
44 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
46 #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */
47 #define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/
52 #define CREG_CCNT 0x30UL /* Collision Counter */
58 #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
63 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
87 /* 0x004-->0x0fc, reserved */
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/linux/drivers/rtc/
H A Drtc-imxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
10 * Since the RTC framework performs API locking via rtc->ops_lock the
17 * DIER (DryIce Interrupt Enable Register) are the only exception. These
36 #define DTCMR 0x00 /* Time Counter MSB Reg */
37 #define DTCLR 0x04 /* Time Counter LSB Reg */
41 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
44 #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
45 #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
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/linux/include/linux/mfd/
H A Dmotorola-cpcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
33 #define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
34 #define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */
35 #define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */
36 #define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */
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/linux/drivers/media/pci/cx88/
H A Dcx88-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * cx88x-hw.h - CX2388x register offsets
5 * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
68 #define MO_PCI_INTMSK 0x200040 // PCI interrupt mask
69 #define MO_PCI_INTSTAT 0x200044 // PCI interrupt status
70 #define MO_PCI_INTMSTAT 0x200048 // PCI interrupt masked status
71 #define MO_VID_INTMSK 0x200050 // Video interrupt mask
72 #define MO_VID_INTSTAT 0x200054 // Video interrupt status
73 #define MO_VID_INTMSTAT 0x200058 // Video interrupt masked status
74 #define MO_VID_INTSSTAT 0x20005C // Video interrupt set status
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/linux/Documentation/devicetree/bindings/timer/
H A Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
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/linux/arch/mips/include/asm/sgi/
H A Dioc.h20 * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
44 volatile u8 istat0; /* Interrupt status zero */
54 volatile u8 imask0; /* Interrupt mask zero */
56 volatile u8 istat1; /* Interrupt status one */
66 volatile u8 imask1; /* Interrupt mask one */
68 volatile u8 vmeistat; /* VME interrupt status */
70 volatile u8 cmeimask0; /* VME interrupt mask zero */
72 volatile u8 cmeimask1; /* VME interrupt mask one */
81 volatile u8 tcnt0; /* counter 0 */
83 volatile u8 tcnt1; /* counter 1 */
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/linux/Documentation/virt/kvm/x86/
H A Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
44 One of the first timer devices available is the programmable interrupt timer,
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
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/linux/arch/mips/include/asm/sn/sn0/
H A Dhubpi.h8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
30 #define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */
65 #define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A)
68 /* Regular Interrupt register checking. */
73 #define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */
74 #define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */
75 #define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */
76 #define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */
82 #define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */
83 #define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */
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/linux/Documentation/devicetree/bindings/rtc/
H A Drenesas,rz-rtca3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RTCA-3 Real Time Clock
10 - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
13 - $ref: rtc.yaml#
18 - enum:
19 - renesas,r9a08g045-rtca3 # RZ/G3S
20 - const: renesas,rz-rtca3
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/linux/drivers/perf/
H A Dfsl_imx9_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/interrupt.h>
42 * 32bit counters monitor counter-specific events in addition to counting reference events
68 * event which corresponding respecitively to counter 2, 3 and 4.
74 * respecitively to counter 2-5.
119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1; in axi_filter_v1()
124 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2; in axi_filter_v2()
128 { .compatible = "fsl,imx91-ddr-pmu", .data = &imx91_devtype_data },
129 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
130 { .compatible = "fsl,imx94-ddr-pmu", .data = &imx94_devtype_data },
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/linux/drivers/gpu/drm/
H A Ddrm_vblank.c91 * "Physical top of display" is the reference point for the high-precision/
99 * with the timing of the hardware programming, an interrupt is usually
101 * The interrupt is in this context named the vblank interrupt.
103 * The vblank interrupt may be fired at different points depending on the
104 * hardware. Some hardware implementations will fire the interrupt when the
105 * new frame start, other implementations will fire the interrupt at different
109 * tear-free display, users must synchronize page flips and/or rendering to
114 * involves filtering out spurious interrupts, keeping race-free blanking
115 * counters, coping with counter wrap-around and resets and keeping use counts.
117 * optionally provide a hardware vertical blanking counter.
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/linux/drivers/clocksource/
H A Dasm9260_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
8 #include <linux/interrupt.h>
19 #define DRIVER_NAME "asm9260-timer"
23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
31 #define HW_IR 0x0000 /* RW. Interrupt */
40 * Timer Counter and the Prescale Counter are synchronously reset on the
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/linux/arch/mips/loongson2ef/common/cs5536/
H A Dcs5536_mfgpt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/interrupt.h>
36 /* disable counter */
43 /* enable counter, comparator2 to event mode, 14.318MHz clock */
55 outw(0, MFGPT0_CNT); /* set counter to 0 */ in mfgpt_timer_set_periodic()
113 cd->cpumask = cpumask_of(cpu); in setup_mfgpt0_timer()
115 cd->max_delta_ns = clockevent_delta2ns(0xffff, cd); in setup_mfgpt0_timer()
116 cd->max_delta_ticks = 0xffff; in setup_mfgpt0_timer()
117 cd->min_delta_ns = clockevent_delta2ns(0xf, cd); in setup_mfgpt0_timer()
118 cd->min_delta_ticks = 0xf; in setup_mfgpt0_timer()
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/linux/drivers/net/ethernet/amd/
H A Dariadne.h4 * © Copyright 1995 by Geert Uytterhoeven (geert@linux-m68k.org)
8 * ----------------------------------------------------------------------------------
13 * Written 1993-94 by Donald Becker.
15 * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller
22 * ----------------------------------------------------------------------------------
28 * ----------------------------------------------------------------------------------
30 * The Ariadne is a Zorro-II board made by Village Tronic. It contains:
32 * - an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both
33 * 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
35 * - an MC68230 Parallel Interface/Timer configured as 2 parallel ports
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