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/linux/kernel/irq/
H A Dmanage.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006 Thomas Gleixner
15 #include <linux/interrupt.h>
42 irq_work_sync(&desc->redirect.work); in synchronize_irqwork()
60 while (irqd_irq_inprogress(&desc->irq_data)) in __synchronize_hardirq()
63 /* Ok, that indicated we're done: double-check carefully. */ in __synchronize_hardirq()
64 guard(raw_spinlock_irqsave)(&desc->lock); in __synchronize_hardirq()
65 inprogress = irqd_irq_inprogress(&desc->irq_data); in __synchronize_hardirq()
85 * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
[all …]
H A Ddevres.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/interrupt.h>
23 free_irq(this->irq, this->dev_id); in devm_irq_release()
30 return this->irq == match->irq && this->dev_id == match->dev_id; in devm_irq_match()
56 return -ENOMEM; in __devm_request_threaded_irq()
68 dr->irq = irq; in __devm_request_threaded_irq()
69 dr->dev_id = dev_id; in __devm_request_threaded_irq()
76 * devm_request_threaded_irq - allocate an interrupt line for a managed device with error logging
77 * @dev: Device to request interrupt for
78 * @irq: Interrupt line to allocate
[all …]
H A Dirq_test.c1 // SPDX-License-Identifier: LGPL-2.1+
6 #include <linux/interrupt.h>
49 virq = irq_domain_alloc_descs(-1, 1, 0, NUMA_NO_NODE, affd); in irq_test_setup_fake_irq()
76 KUNIT_EXPECT_EQ(test, desc->depth, 0); in irq_disable_depth_test()
79 KUNIT_EXPECT_EQ(test, desc->depth, 1); in irq_disable_depth_test()
82 KUNIT_EXPECT_EQ(test, desc->depth, 0); in irq_disable_depth_test()
100 KUNIT_EXPECT_EQ(test, desc->depth, 0); in irq_free_disabled_test()
103 KUNIT_EXPECT_EQ(test, desc->depth, 1); in irq_free_disabled_test()
106 KUNIT_EXPECT_GE(test, desc->depth, 1); in irq_free_disabled_test()
110 KUNIT_EXPECT_EQ(test, desc->depth, 0); in irq_free_disabled_test()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller is a simple interrupt controller present on
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
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H A Dbrcm,bcm6345-l1-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6345-style Level 1 interrupt controller
10 - Simon Arlott <simon@octiron.net>
13 This block is a first level interrupt controller that is typically connected
18 - 32, 64 or 128 incoming level IRQ lines
20 - Most onchip peripherals are wired directly to an L1 input
22 - A separate instance of the register set for each CPU, allowing individual
[all …]
/linux/drivers/infiniband/hw/hfi1/
H A Daffinity.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
8 #include <linux/interrupt.h>
12 #include "affinity.h"
35 cpumask_clear(&set->mask); in init_cpu_mask_set()
36 cpumask_clear(&set->used); in init_cpu_mask_set()
37 set->gen = 0; in init_cpu_mask_set()
43 if (cpumask_equal(&set->mask, &set->used)) { in _cpu_mask_set_gen_inc()
48 set->gen++; in _cpu_mask_set_gen_inc()
49 cpumask_clear(&set->used); in _cpu_mask_set_gen_inc()
[all …]
/linux/drivers/irqchip/
H A Dirq-bcm7038-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7038 style Level 1 interrupt controller driver
14 #include <linux/interrupt.h>
47 u8 affinity[MAX_WORDS * IRQS_PER_WORD]; member
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
88 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
94 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
121 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
123 cpu = intc->cpus[0]; in bcm7038_l1_irq_handle()
128 for (idx = 0; idx < intc->n_words; idx++) { in bcm7038_l1_irq_handle()
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/linux/arch/powerpc/sysdev/xics/
H A Dxics-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/interrupt.h>
60 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); in xics_update_irq_servers()
68 /* Global interrupt distribution server is specified in the last in xics_update_irq_servers()
69 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last in xics_update_irq_servers()
96 index = (1UL << xics_interrupt_server_size) - 1 - gserver; in xics_set_cpu_giq()
100 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", in xics_set_cpu_giq()
107 icp_ops->set_priority(LOWEST_PRIORITY); in xics_setup_cpu()
114 pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec); in xics_mask_unknown_vec()
118 xics_ics->mask_unknown(xics_ics, vec); in xics_mask_unknown_vec()
[all …]
/linux/include/linux/
H A Dirqdomain.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * irq_domain - IRQ Translation Domains
5 * See Documentation/core-api/irq/irq-domain.rst for the details.
16 #include <linux/radix-tree.h>
32 * struct irq_fwspec - generic IRQ specifier structure
34 * @fwnode: Pointer to a firmware-specific descriptor
35 * @param_count: Number of device-specific parameters
36 * @param: Device-specific parameters
39 * pass a device-specific description of an interrupt.
48 * struct irq_fwspec_info - firmware provided IRQ information structure
[all …]
H A Drseq_types.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 * struct rseq_event - Storage for rseq related event management
25 * @user_irq: True on interrupt entry from user mode
64 * struct rseq_ids - Cache for ids, which need to be updated
66 * compiler emit a single compare on 64-bit
85 * union rseq_slice_state - Status information for rseq time slice extension
99 * struct rseq_slice - Status information for rseq time slice extension
111 * struct rseq_data - Storage for all rseq related data
141 * struct sched_mm_cid - Storage for per task MM CID data
154 * struct mm_cid_pcpu - Storage for per CPU MM_CID data
[all …]
/linux/lib/
H A Dcpu_rmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cpu_rmap.c: CPU affinity reverse-map support
8 #include <linux/interrupt.h>
13 * objects with CPU affinities. This can be seen as a reverse-map of
14 * CPU affinity. However, we do not assume that the object affinities
21 * alloc_cpu_rmap - allocate CPU affinity reverse-map
39 rmap = kzalloc(obj_offset + size * sizeof(rmap->obj[0]), flags); in alloc_cpu_rmap()
43 kref_init(&rmap->refcount); in alloc_cpu_rmap()
44 rmap->obj = (void **)((char *)rmap + obj_offset); in alloc_cpu_rmap()
50 * any newly-hotplugged CPUs to have some object assigned. in alloc_cpu_rmap()
[all …]
/linux/arch/x86/kernel/apic/
H A Dvector.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/interrupt.h>
78 info->mask = mask; in init_irq_alloc_info()
94 while (irqd->parent_data) in apic_chip_data()
95 irqd = irqd->parent_data; in apic_chip_data()
97 return irqd->chip_data; in apic_chip_data()
104 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
119 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
135 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
[all …]
/linux/arch/mips/sibyte/sb1250/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/interrupt.h>
26 * These are the routines that handle all the low level interrupt stuff.
27 * Actions handled here are: initialization of the interrupt map, requesting of
28 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
29 * for interrupt lines
74 unsigned int irq = d->irq; in sb1250_set_affinity()
83 /* Protect against other affinity changers and IMR manipulation */ in sb1250_set_affinity()
114 unsigned int irq = d->irq; in disable_sb1250_irq()
121 unsigned int irq = d->irq; in enable_sb1250_irq()
[all …]
/linux/drivers/perf/
H A Darm_pmu.c1 // SPDX-License-Identifier: GPL-2.0-only
29 static int armpmu_count_irq_users(const struct cpumask *affinity,
70 if (armpmu_count_irq_users(&armpmu->supported_cpus, irq) == 1) in armpmu_free_percpu_pmuirq()
97 if (armpmu_count_irq_users(&armpmu->supported_cpus, irq) == 1) in armpmu_free_percpu_pmunmi()
114 if (event->hw.flags & ARMPMU_EVT_64BIT) in arm_pmu_event_max_period()
116 else if (event->hw.flags & ARMPMU_EVT_63BIT) in arm_pmu_event_max_period()
118 else if (event->hw.flags & ARMPMU_EVT_47BIT) in arm_pmu_event_max_period()
135 return -EINVAL; in armpmu_map_cache_event()
139 return -EINVAL; in armpmu_map_cache_event()
143 return -EINVAL; in armpmu_map_cache_event()
[all …]
/linux/Documentation/virt/hyperv/
H A Dvpci.rst1 .. SPDX-License-Identifier: GPL-2.0
3 PCI pass-thru devices
5 In a Hyper-V guest VM, PCI pass-thru devices (also called
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 …tps://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-deploying-devi…
23 and for GPUs. A similar mechanism for NICs is called SR-IOV
25 driver to interact directly with the hardware. See Hyper-V
26 public documentation here: `SR-IOV`_
28 .. _SR-IOV: https://learn.microsoft.com/en-us/windows-hardware/drivers/network/overview-of-single-r…
[all …]
/linux/arch/mips/sibyte/bcm1480/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/interrupt.h>
27 * These are the routines that handle all the low level interrupt stuff.
28 * Actions handled here are: initialization of the interrupt map, requesting of
29 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
30 * for interrupt lines
51 irq -= BCM1480_NR_IRQS_HALF; in bcm1480_mask_irq()
68 irq -= BCM1480_NR_IRQS_HALF; in bcm1480_unmask_irq()
80 unsigned int irq_dirty, irq = d->irq; in bcm1480_set_affinity()
90 /* Protect against other affinity changers and IMR manipulation */ in bcm1480_set_affinity()
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf500.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a5";
28 intc: interrupt-controller@40003000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
[all …]
/linux/drivers/resctrl/
H A Dmpam_devices.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/interrupt.h>
44 * mpam_enabled key is enabled these lists are read-only,
45 * unless the error interrupt disables the driver.
88 * mpam_is_enabled(). The disable call after an error interrupt makes
96 * their RIS index. These share a base-address, interrupts and some MMIO
102 * are from different MSC, so have different base-address, interrupts etc.
114 * e.g. The L2 may have one MSC and two RIS, one for cache-controls another
126 * The same MSC may exist under different class->component->vmsc paths, but the
136 init_llist_node(&garbage->llist); in init_garbage()
[all …]
/linux/arch/arc/kernel/
H A Dmcip.c1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <asm/irqflags-arcv2.h>
71 * STATUS32[H]/actionpoint/breakpoint/self-halt in mcip_update_debug_halt_mask()
111 * If receiver already has a pending interrupt, elide sending this one. in mcip_ipi_send()
181 * ARCv2 Interrupt Distribution Unit (IDU)
184 * -dynamic routing (IRQ affinity)
185 * -load balancing (Round Robin interrupt distribution)
186 * -1:N distribution
232 idu_irq_mask_raw(data->hwirq); in idu_irq_mask()
240 __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); in idu_irq_unmask()
[all …]
/linux/samples/pktgen/
H A Dpktgen_sample06_numa_awared_queue_irq_affinity.sh5 # * bound devices queue's irq affinity to the threads, 1:1 mapping
14 # Required param: -i dev in $DEV
21 [ -z "$COUNT" ] && COUNT="20000000" # Zero means indefinitely
22 [ -z "$CLONE_SKB" ] && CLONE_SKB="0"
32 [ $THREADS -gt ${#irq_array[*]} -o $THREADS -gt ${#cpu_array[*]} ] && \
36 if [ -z "$DEST_IP" ]; then
37 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1"
39 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
40 if [ -n "$DEST_IP" ]; then
42 read -r DST_MIN DST_MAX <<< $(parse_addr${IP6} $DEST_IP)
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
[all …]
/linux/arch/arm/mach-versatile/
H A Dspc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include <linux/interrupt.h>
28 #define SPCLOG "vexpress-spc: "
39 /* SPC wake-up IRQs status and mask */
46 /* SPC per-CPU mailboxes */
68 /* wake-up interrupt masks */
71 /* TC2 static dual-cluster configuration */
75 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
113 return cluster == info->a15_clusid; in cluster_is_a15()
[all …]
/linux/arch/alpha/kernel/
H A Dsys_titan.c1 // SPDX-License-Identifier: GPL-2.0
55 * Need SMP-safe access to interrupt CSRs
83 dim0 = &cchip->dim0.csr; in titan_update_irq_hw()
84 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()
85 dim2 = &cchip->dim2.csr; in titan_update_irq_hw()
86 dim3 = &cchip->dim3.csr; in titan_update_irq_hw()
103 dimB = &cchip->dim0.csr; in titan_update_irq_hw()
104 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()
105 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()
106 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
62 cci-control-port = <&cci_control0>;
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
[all …]

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