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/linux/kernel/irq/
H A Dcpuhotplug.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic cpu hotunplug interrupt migration code copied from the
12 #include <linux/interrupt.h>
19 /* For !GENERIC_IRQ_EFFECTIVE_AFF_MASK this looks at general affinity mask */
27 * The cpumask_empty() check is a workaround for interrupt chips, in irq_needs_fixup()
28 * which do not implement effective affinity, but the architecture has in irq_needs_fixup()
29 * enabled the config switch. Use the general affinity mask instead. in irq_needs_fixup()
45 pr_warn("Eff. affinity in irq_needs_fixup()
58 const struct cpumask *affinity; migrate_one_irq() local
207 const struct cpumask *affinity = irq_data_get_affinity_mask(data); irq_restore_affinity_of_irq() local
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H A Dmanage.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006 Thomas Gleixner
15 #include <linux/interrupt.h>
42 irq_work_sync(&desc->redirect.work); in synchronize_irqwork()
60 while (irqd_irq_inprogress(&desc->irq_data)) in __synchronize_hardirq()
63 /* Ok, that indicated we're done: double-check carefully. */ in __synchronize_hardirq()
64 guard(raw_spinlock_irqsave)(&desc->lock); in __synchronize_hardirq()
65 inprogress = irqd_irq_inprogress(&desc->irq_data); in __synchronize_hardirq()
85 * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
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H A Dirqdesc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 * This file contains the interrupt descriptor management code. Detailed
7 * information is available in Documentation/core-api/genericirq.rst
13 #include <linux/interrupt.h>
23 * lockdep: we want to handle all irq_desc locks as a single lock-class:
57 if (!zalloc_cpumask_var_node(&desc->irq_common_data.affinity, in alloc_masks()
59 return -ENOMEM; in alloc_masks()
62 if (!zalloc_cpumask_var_node(&desc->irq_common_data.effective_affinity, in alloc_masks()
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H A Daffinity.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2016-2017 Christoph Hellwig.
6 #include <linux/interrupt.h>
14 affd->nr_sets = 1; in default_calc_sets()
15 affd->set_size[0] = affvecs; in default_calc_sets()
19 * irq_create_affinity_masks - Create affinity masks for multiqueue spreading
21 * @affd: Description of the affinity requirements
32 * Determine the number of vectors which need interrupt affinities in irq_create_affinity_masks()
37 if (nvecs > affd->pre_vectors + affd->post_vectors) in irq_create_affinity_masks()
38 affvecs = nvecs - affd->pre_vectors - affd->post_vectors; in irq_create_affinity_masks()
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H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
26 * struct msi_device_data - MSI per device data
40 * struct msi_ctrl - MSI internal management control structure
45 * than the range due to PCI/multi-MSI.
55 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
66 * msi_alloc_desc - Allocate an initialized msi_desc
69 * @affinity: Optional pointer to an affinity mask array size of @nvec
71 * If @affinity is not %NULL then an affinity array[@nvec] is allocated
72 * and the affinity masks and flags from @affinity are copied.
77 const struct irq_affinity_desc *affinity) in msi_alloc_desc() argument
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H A Dirqdomain.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
30 bool realloc, const struct irq_affinity_desc *affinity);
54 return fwid->name; in irqchip_fwnode_get_name()
61 return fwid->parent; in irqchip_fwnode_get_parent()
71 * __irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for
76 * @pa: Optional user-provided physical address
102 n = kasprintf(GFP_KERNEL, "%s-%d", name, id); in __irq_domain_alloc_fwnode()
115 fwid->type = type; in __irq_domain_alloc_fwnode()
116 fwid->name = n; in __irq_domain_alloc_fwnode()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 # Supports effective affinity mask
26 # Support for delayed migration from interrupt context
34 # Alpha specific irq affinity mechanism
38 # Interrupt injection mechanism
46 # Generic configurable interrupt chip implementation
51 # Generic irq_domain hw <-
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H A Ddevres.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/interrupt.h>
23 free_irq(this->irq, this->dev_id); in devm_irq_release()
30 return this->irq == match->irq && this->dev_id == match->dev_id; in devm_irq_match()
56 return -ENOMEM; in __devm_request_threaded_irq()
68 dr->irq = irq; in __devm_request_threaded_irq()
69 dr->dev_id = dev_id; in __devm_request_threaded_irq()
76 * devm_request_threaded_irq - allocate an interrupt line for a managed device with error logging
77 * @dev: Device to request interrupt for
78 * @irq: Interrupt line to allocate
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H A Dchip.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 * This file contains the core interrupt handling code, for irq-chip based
8 * Documentation/core-api/genericirq.rst
14 #include <linux/interrupt.h>
37 * irq_set_chip - se
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H A Dirq_test.c1 // SPDX-License-Identifier: LGPL-2.1+
6 #include <linux/interrupt.h>
49 virq = irq_domain_alloc_descs(-1, 1, 0, NUMA_NO_NODE, affd); in irq_test_setup_fake_irq()
76 KUNIT_EXPECT_EQ(test, desc->depth, 0); in irq_disable_depth_test()
79 KUNIT_EXPECT_EQ(test, desc->depth, 1); in irq_disable_depth_test()
82 KUNIT_EXPECT_EQ(test, desc->depth, 0); in irq_disable_depth_test()
100 KUNIT_EXPECT_EQ(test, desc->depth, 0); in irq_free_disabled_test()
103 KUNIT_EXPECT_EQ(test, desc->depth, 1); in irq_free_disabled_test()
106 KUNIT_EXPECT_GE(test, desc->depth, 1); in irq_free_disabled_test()
110 KUNIT_EXPECT_EQ(test, desc->depth, 0); in irq_free_disabled_test()
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/linux/drivers/pci/msi/
H A Dapi.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCI MSI/MSI-X — Exported APIs for device drivers
5 * Copyright (C) 2003-2004 Intel
17 * pci_enable_msi() - Enable MSI interrupt mode on device
21 * allocate a single interrupt vector. On success, the allocated vector
22 * Linux IRQ will be saved at @dev->irq. The driver must invoke
40 * pci_disable_msi() - Disable MSI interrupt mode on device
43 * Legacy device driver API to disable MSI interrupt mode on device,
44 * free earlier allocated interrupt vectors, and restore INTx emulation.
45 * The PCI device Linux IRQ (@dev->irq) is restored to its default
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller is a simple interrupt controller present on
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
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/linux/drivers/infiniband/hw/hfi1/
H A Daffinity.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
8 #include <linux/interrupt.h>
12 #include "affinity.h"
35 cpumask_clear(&set->mask); in init_cpu_mask_set()
36 cpumask_clear(&set->used); in init_cpu_mask_set()
37 set->gen = 0; in init_cpu_mask_set()
43 if (cpumask_equal(&set->mask, &set->used)) { in _cpu_mask_set_gen_inc()
48 set->gen++; in _cpu_mask_set_gen_inc()
49 cpumask_clear(&set->used); in _cpu_mask_set_gen_inc()
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/linux/drivers/irqchip/
H A Dirq-bcm7038-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7038 style Level 1 interrupt controller driver
14 #include <linux/interrupt.h>
47 u8 affinity[MAX_WORDS * IRQS_PER_WORD]; member
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
88 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
94 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
121 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
123 cpu = intc->cpus[0]; in bcm7038_l1_irq_handle()
128 for (idx = 0; idx < intc->n_words; idx++) { in bcm7038_l1_irq_handle()
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H A Dirq-msi-lib.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/irqchip/irq-msi-lib.h>
10 * msi_lib_init_dev_msi_info - Domain info setup for MSI domains
30 const struct msi_parent_ops *pops = real_parent->msi_parent_ops; in msi_lib_init_dev_msi_info()
31 struct irq_chip *chip = info->chip; in msi_lib_init_dev_msi_info()
41 * possible to stack MSI parents. See x86 vector -> irq remapping in msi_lib_init_dev_msi_info()
43 if (domain->bus_token == pops->bus_select_token) { in msi_lib_init_dev_msi_info()
51 required_flags = pops->required_flags; in msi_lib_init_dev_msi_info()
54 switch(info->bus_token) { in msi_lib_init_dev_msi_info()
64 * set. It's sole purpose is to create a dumb interrupt in msi_lib_init_dev_msi_info()
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/linux/arch/powerpc/sysdev/xics/
H A Dxics-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/interrupt.h>
60 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); in xics_update_irq_servers()
68 /* Global interrupt distribution server is specified in the last in xics_update_irq_servers()
69 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last in xics_update_irq_servers()
96 index = (1UL << xics_interrupt_server_size) - 1 - gserver; in xics_set_cpu_giq()
100 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", in xics_set_cpu_giq()
107 icp_ops->set_priority(LOWEST_PRIORITY); in xics_setup_cpu()
114 pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec); in xics_mask_unknown_vec()
118 xics_ics->mask_unknown(xics_ics, vec); in xics_mask_unknown_vec()
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/linux/arch/alpha/kernel/
H A Dsys_dp264.c1 // SPDX-License-Identifier: GPL-2.0
68 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
70 dim2 = &cchip->dim2.csr; in tsunami_update_irq_hw()
71 dim3 = &cchip->dim3.csr; in tsunami_update_irq_hw()
88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()
89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()
90 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()
91 else dimB = &cchip->dim3.csr; in tsunami_update_irq_hw()
103 cached_irq_mask |= 1UL << d->irq; in dp264_enable_irq()
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/linux/lib/
H A Dcpu_rmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cpu_rmap.c: CPU affinity reverse-map support
8 #include <linux/interrupt.h>
13 * objects with CPU affinities. This can be seen as a reverse-map of
14 * CPU affinity. However, we do not assume that the object affinities
21 * alloc_cpu_rmap - allocate CPU affinity reverse-map
39 rmap = kzalloc(obj_offset + size * sizeof(rmap->obj[0]), flags); in alloc_cpu_rmap()
43 kref_init(&rmap->refcount); in alloc_cpu_rmap()
44 rmap->obj = (void **)((char *)rmap + obj_offset); in alloc_cpu_rmap()
50 * any newly-hotplugged CPUs to have some object assigned. in alloc_cpu_rmap()
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/linux/drivers/iommu/
H A Dhyperv-iommu.c1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V stub IOMMU driver.
12 #include <linux/interrupt.h>
30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
42 struct irq_data *parent = data->parent_data; in hyperv_ir_set_affinity()
46 /* Return error If new irq affinity is out of ioapic_max_cpumask. */ in hyperv_ir_set_affinity()
48 return -EINVAL; in hyperv_ir_set_affinity()
50 ret = parent->chip->irq_set_affinity(parent, mask, force); in hyperv_ir_set_affinity()
60 .name = "HYPERV-IR",
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/linux/arch/x86/kernel/apic/
H A Dvector.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/interrupt.h>
78 info->mask = mask; in init_irq_alloc_info()
94 while (irqd->parent_data) in apic_chip_data()
95 irqd = irqd->parent_data; in apic_chip_data()
97 return irqd->chip_data; in apic_chip_data()
104 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
119 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
135 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
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/linux/drivers/base/
H A Dplatform.c1 // SPDX-License-Identifier: GPL-2.0
3 * platform.c - platform 'pseudo' bus for legacy devices
5 * Copyright (c) 2002-3 Patrick Mochel
6 * Copyright (c) 2002-3 Open Source Development Labs
8 * Please see Documentation/driver-api/driver-model/platform.rst for more
18 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
28 #include <linux/clk/clk-conf.h>
34 #include <linux/dma-map-ops.h>
48 * platform_get_resource - get a resource for a device
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/linux/arch/mips/sibyte/sb1250/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/interrupt.h>
26 * These are the routines that handle all the low level interrupt stuff.
27 * Actions handled here are: initialization of the interrupt map, requesting of
28 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
29 * for interrupt lines
74 unsigned int irq = d->irq; in sb1250_set_affinity()
83 /* Protect against other affinity changers and IMR manipulation */ in sb1250_set_affinity()
114 unsigned int irq = d->irq; in disable_sb1250_irq()
121 unsigned int irq = d->irq; in enable_sb1250_irq()
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/linux/drivers/perf/
H A Darm_pmu.c1 // SPDX-License-Identifier: GPL-2.0-only
29 static int armpmu_count_irq_users(const struct cpumask *affinity,
70 if (armpmu_count_irq_users(&armpmu->supported_cpus, irq) == 1) in armpmu_free_percpu_pmuirq()
97 if (armpmu_count_irq_users(&armpmu->supported_cpus, irq) == 1) in armpmu_free_percpu_pmunmi()
114 if (event->hw.flags & ARMPMU_EVT_64BIT) in arm_pmu_event_max_period()
116 else if (event->hw.flags & ARMPMU_EVT_63BIT) in arm_pmu_event_max_period()
118 else if (event->hw.flags & ARMPMU_EVT_47BIT) in arm_pmu_event_max_period()
135 return -EINVAL; in armpmu_map_cache_event()
139 return -EINVAL; in armpmu_map_cache_event()
143 return -EINVAL; in armpmu_map_cache_event()
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/linux/Documentation/virt/hyperv/
H A Dvpci.rst1 .. SPDX-License-Identifier: GPL-2.0
3 PCI pass-thru devices
5 In a Hyper-V guest VM, PCI pass-thru devices (also called
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 …tps://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-deploying-devi…
23 and for GPUs. A similar mechanism for NICs is called SR-IOV
25 driver to interact directly with the hardware. See Hyper-V
26 public documentation here: `SR-IOV`_
28 .. _SR-IOV: https://learn.microsoft.com/en-us/windows-hardware/drivers/network/overview-of-single-r…
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynos990.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
8 #include <dt-bindings/clock/samsung,exynos990.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <1>;
16 interrupt-parent = <&gic>;
29 #address-cells = <1>;
30 #size-cells = <0>;
32 cpu-map {
74 compatible = "arm,cortex-a55";
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