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/linux/kernel/irq/
H A Dcpuhotplug.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic cpu hotunplug interrupt migration code copied from the
12 #include <linux/interrupt.h>
19 /* For !GENERIC_IRQ_EFFECTIVE_AFF_MASK this looks at general affinity mask */
27 * The cpumask_empty() check is a workaround for interrupt chips, in irq_needs_fixup()
28 * which do not implement effective affinity, but the architecture has in irq_needs_fixup()
29 * enabled the config switch. Use the general affinity mask instead. in irq_needs_fixup()
45 pr_warn("Eff. affinity %*pbl of IRQ %u contains only offline CPUs after offlining CPU %u\n", in irq_needs_fixup()
46 cpumask_pr_args(m), d->irq, cpu); in irq_needs_fixup()
58 const struct cpumask *affinity; in migrate_one_irq() local
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H A Daffinity.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2016-2017 Christoph Hellwig.
6 #include <linux/interrupt.h>
14 affd->nr_sets = 1; in default_calc_sets()
15 affd->set_size[0] = affvecs; in default_calc_sets()
19 * irq_create_affinity_masks - Create affinity masks for multiqueue spreading
21 * @affd: Description of the affinity requirements
32 * Determine the number of vectors which need interrupt affinities in irq_create_affinity_masks()
37 if (nvecs > affd->pre_vectors + affd->post_vectors) in irq_create_affinity_masks()
38 affvecs = nvecs - affd->pre_vectors - affd->post_vectors; in irq_create_affinity_masks()
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H A Dmsi.c1 // SPDX-License-Identifier: GPL-2.0
25 * struct msi_device_data - MSI per device data
39 * struct msi_ctrl - MSI internal management control structure
44 * than the range due to PCI/multi-MSI.
54 #define MSI_XA_MAX_INDEX (ULONG_MAX - 1)
64 * msi_alloc_desc - Allocate an initialized msi_desc
67 * @affinity: Optional pointer to an affinity mask array size of @nvec
69 * If @affinity is not %NULL then an affinity array[@nvec] is allocated
70 * and the affinity masks and flags from @affinity are copied.
75 const struct irq_affinity_desc *affinity) in msi_alloc_desc() argument
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H A Dproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2004 Linus Torvalds, Ingo Molnar
12 #include <linux/interrupt.h>
22 * concurrent free of the interrupt descriptor. remove_proc_entry()
26 * We remove the proc entries first and then delete the interrupt
40 AFFINITY, enumerator
48 struct irq_desc *desc = irq_to_desc((long)m->private); in show_irq_affinity()
52 case AFFINITY: in show_irq_affinity()
54 mask = desc->irq_common_data.affinity; in show_irq_affinity()
55 if (irq_move_pending(&desc->irq_data)) in show_irq_affinity()
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H A Dirqdomain.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/interrupt.h>
30 bool realloc, const struct irq_affinity_desc *affinity);
53 return fwid->name; in irqchip_fwnode_get_name()
62 * __irq_domain_alloc_fwnode - Allocate a fwnode_handle suitable for
67 * @pa: Optional user-provided physical address
91 n = kasprintf(GFP_KERNEL, "%s-%d", name, id); in __irq_domain_alloc_fwnode()
104 fwid->type = type; in __irq_domain_alloc_fwnode()
105 fwid->name = n; in __irq_domain_alloc_fwnode()
106 fwid->pa = pa; in __irq_domain_alloc_fwnode()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller is a simple interrupt controller present on
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
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H A Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple Interrupt Controller 2
10 - Hector Martin <marcan@marcan.st>
13 The Apple Interrupt Controller 2 is a simple interrupt controller present on
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
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H A Darm,gic-v3.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 3
10 - Marc Zyngier <maz@kernel.org>
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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/linux/drivers/infiniband/hw/hfi1/
H A Daffinity.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
8 #include <linux/interrupt.h>
12 #include "affinity.h"
35 cpumask_clear(&set->mask); in init_cpu_mask_set()
36 cpumask_clear(&set->used); in init_cpu_mask_set()
37 set->gen = 0; in init_cpu_mask_set()
43 if (cpumask_equal(&set->mask, &set->used)) { in _cpu_mask_set_gen_inc()
48 set->gen++; in _cpu_mask_set_gen_inc()
49 cpumask_clear(&set->used); in _cpu_mask_set_gen_inc()
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/linux/include/linux/
H A Dinterrupt.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* interrupt.h */
26 * linux/ioport.h to select the interrupt line behaviour. When
27 * requesting an interrupt without specifying a IRQF_TRIGGER, the
44 * IRQF_SHARED - allow sharing the irq among several devices
45 * IRQF_PROBE_SHARED - set by callers when they expect sharing mismatches to occur
46 * IRQF_TIMER - Flag to mark this interrupt as timer interrupt
47 * IRQF_PERCPU - Interrupt is per cpu
48 * IRQF_NOBALANCING - Flag to exclude this interrupt from irq balancing
49 * IRQF_IRQPOLL - Interrupt is used for polling (only the interrupt that is
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H A Dirqdesc.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 * struct irqstat - interrupt statistics
22 * @cnt: real-time interrupt count
23 * @ref: snapshot of interrupt count
33 * struct irq_desc - interrupt descriptor
36 * @handle_irq: highlevel irq-events handler
40 * @depth: disable-depth, for nested irq_disable() calls
42 * @tot_count: stats field for non-percpu irqs
49 * @affinity_hint: hint to user space for preferred irq affinity
50 * @affinity_notify: context for notification of affinity changes
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/linux/drivers/perf/
H A Darm_pmu_platform.c1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return of_property_present(node, "interrupt-affinity"); in pmu_has_irq_affinity()
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/linux/drivers/irqchip/
H A Dirq-bcm7038-l1.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Broadcom BCM7038 style Level 1 interrupt controller driver
14 #include <linux/interrupt.h>
47 u8 affinity[MAX_WORDS * IRQS_PER_WORD]; member
82 return (0 * intc->n_words + word) * sizeof(u32); in reg_status()
88 return (1 * intc->n_words + word) * sizeof(u32); in reg_mask_status()
94 return (2 * intc->n_words + word) * sizeof(u32); in reg_mask_set()
100 return (3 * intc->n_words + word) * sizeof(u32); in reg_mask_clr()
127 cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; in bcm7038_l1_irq_handle()
129 cpu = intc->cpus[0]; in bcm7038_l1_irq_handle()
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/linux/arch/powerpc/sysdev/xics/
H A Dxics-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/interrupt.h>
60 ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen); in xics_update_irq_servers()
68 /* Global interrupt distribution server is specified in the last in xics_update_irq_servers()
69 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last in xics_update_irq_servers()
96 index = (1UL << xics_interrupt_server_size) - 1 - gserver; in xics_set_cpu_giq()
100 WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n", in xics_set_cpu_giq()
107 icp_ops->set_priority(LOWEST_PRIORITY); in xics_setup_cpu()
114 pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec); in xics_mask_unknown_vec()
118 xics_ics->mask_unknown(xics_ics, vec); in xics_mask_unknown_vec()
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/linux/lib/
H A Dcpu_rmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cpu_rmap.c: CPU affinity reverse-map support
8 #include <linux/interrupt.h>
13 * objects with CPU affinities. This can be seen as a reverse-map of
14 * CPU affinity. However, we do not assume that the object affinities
21 * alloc_cpu_rmap - allocate CPU affinity reverse-map
39 rmap = kzalloc(obj_offset + size * sizeof(rmap->obj[0]), flags); in alloc_cpu_rmap()
43 kref_init(&rmap->refcount); in alloc_cpu_rmap()
44 rmap->obj = (void **)((char *)rmap + obj_offset); in alloc_cpu_rmap()
50 * any newly-hotplugged CPUs to have some object assigned. in alloc_cpu_rmap()
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/linux/arch/alpha/kernel/
H A Dsys_dp264.c1 // SPDX-License-Identifier: GPL-2.0
68 dim0 = &cchip->dim0.csr; in tsunami_update_irq_hw()
69 dim1 = &cchip->dim1.csr; in tsunami_update_irq_hw()
70 dim2 = &cchip->dim2.csr; in tsunami_update_irq_hw()
71 dim3 = &cchip->dim3.csr; in tsunami_update_irq_hw()
88 if (bcpu == 0) dimB = &cchip->dim0.csr; in tsunami_update_irq_hw()
89 else if (bcpu == 1) dimB = &cchip->dim1.csr; in tsunami_update_irq_hw()
90 else if (bcpu == 2) dimB = &cchip->dim2.csr; in tsunami_update_irq_hw()
91 else dimB = &cchip->dim3.csr; in tsunami_update_irq_hw()
103 cached_irq_mask |= 1UL << d->irq; in dp264_enable_irq()
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H A Dsys_titan.c1 // SPDX-License-Identifier: GPL-2.0
55 * Need SMP-safe access to interrupt CSRs
83 dim0 = &cchip->dim0.csr; in titan_update_irq_hw()
84 dim1 = &cchip->dim1.csr; in titan_update_irq_hw()
85 dim2 = &cchip->dim2.csr; in titan_update_irq_hw()
86 dim3 = &cchip->dim3.csr; in titan_update_irq_hw()
103 dimB = &cchip->dim0.csr; in titan_update_irq_hw()
104 if (bcpu == 1) dimB = &cchip->dim1.csr; in titan_update_irq_hw()
105 else if (bcpu == 2) dimB = &cchip->dim2.csr; in titan_update_irq_hw()
106 else if (bcpu == 3) dimB = &cchip->dim3.csr; in titan_update_irq_hw()
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/linux/arch/arm64/boot/dts/apple/
H A Dt6001.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/apple-aic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/apple.h>
15 #include "multi-die-cpp.h"
17 #include "t600x-common.dtsi"
20 compatible = "apple,t6001", "apple,arm-platform";
23 compatible = "simple-bus";
24 #address-cells = <2>;
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/linux/arch/mips/sibyte/sb1250/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/interrupt.h>
26 * These are the routines that handle all the low level interrupt stuff.
27 * Actions handled here are: initialization of the interrupt map, requesting of
28 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
29 * for interrupt lines
74 unsigned int irq = d->irq; in sb1250_set_affinity()
83 /* Protect against other affinity changers and IMR manipulation */ in sb1250_set_affinity()
114 unsigned int irq = d->irq; in disable_sb1250_irq()
121 unsigned int irq = d->irq; in enable_sb1250_irq()
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/linux/Documentation/virt/hyperv/
H A Dvpci.rst1 .. SPDX-License-Identifier: GPL-2.0
3 PCI pass-thru devices
5 In a Hyper-V guest VM, PCI pass-thru devices (also called
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 …tps://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-deploying-devi…
23 and for GPUs. A similar mechanism for NICs is called SR-IOV
25 driver to interact directly with the hardware. See Hyper-V
26 public documentation here: `SR-IOV`_
28 .. _SR-IOV: https://learn.microsoft.com/en-us/windows-hardware/drivers/network/overview-of-single-r…
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/linux/arch/mips/sibyte/bcm1480/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/interrupt.h>
27 * These are the routines that handle all the low level interrupt stuff.
28 * Actions handled here are: initialization of the interrupt map, requesting of
29 * interrupt lines by handlers, dispatching if interrupts to handlers, probing
30 * for interrupt lines
51 irq -= BCM1480_NR_IRQS_HALF; in bcm1480_mask_irq()
68 irq -= BCM1480_NR_IRQS_HALF; in bcm1480_unmask_irq()
80 unsigned int irq_dirty, irq = d->irq; in bcm1480_set_affinity()
90 /* Protect against other affinity changers and IMR manipulation */ in bcm1480_set_affinity()
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/linux/samples/pktgen/
H A Dpktgen_sample06_numa_awared_queue_irq_affinity.sh5 # * bound devices queue's irq affinity to the threads, 1:1 mapping
14 # Required param: -i dev in $DEV
21 [ -z "$COUNT" ] && COUNT="20000000" # Zero means indefinitely
22 [ -z "$CLONE_SKB" ] && CLONE_SKB="0"
32 [ $THREADS -gt ${#irq_array[*]} -o $THREADS -gt ${#cpu_array[*]} ] && \
36 if [ -z "$DEST_IP" ]; then
37 [ -z "$IP6" ] && DEST_IP="198.18.0.42" || DEST_IP="FD00::1"
39 [ -z "$DST_MAC" ] && DST_MAC="90:e2:ba:ff:ff:ff"
40 if [ -n "$DEST_IP" ]; then
42 read -r DST_MIN DST_MAX <<< $(parse_addr${IP6} $DEST_IP)
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/linux/arch/arm/mach-versatile/
H A Dspc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include <linux/interrupt.h>
28 #define SPCLOG "vexpress-spc: "
39 /* SPC wake-up IRQs status and mask */
46 /* SPC per-CPU mailboxes */
68 /* wake-up interrupt masks */
71 /* TC2 static dual-cluster configuration */
75 * Even though the SPC takes max 3-5 ms to complete any OPP/COMMS
113 return cluster == info->a15_clusid; in cluster_is_a15()
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/linux/arch/arm64/boot/dts/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
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/linux/Documentation/virt/kvm/devices/
H A Darm-vgic-v3.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ARM Virtual Generic Interrupt Controller v3 and later (VGICv3)
9 - KVM_DEV_TYPE_ARM_VGIC_V3 ARM Generic Interrupt Controller v3.0
12 will act as the VM interrupt controller, requiring emulated user-space devices
23 KVM_VGIC_V3_ADDR_TYPE_DIST (rw, 64-bit)
28 KVM_VGIC_V3_ADDR_TYPE_REDIST (rw, 64-bit)
35 KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION (rw, 64-bit)
38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
41 - index encodes the unique redistributor region index
42 - flags: reserved for future use, currently 0
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