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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
16 - Vladimir Oltean <vladimir.oltean@nxp.com>
21 - nxp,sja1105e
22 - nxp,sja1105t
23 - nxp,sja1105p
24 - nxp,sja1105q
25 - nxp,sja1105r
[all …]
H A Dvitesse,vsc73xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
[all …]
H A Dmicrochip,lan937x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - UNGLinuxDriver@microchip.com
13 - $ref: dsa.yaml#/$defs/ethernet-ports
18 - microchip,lan9370
19 - microchip,lan9371
20 - microchip,lan9372
21 - microchip,lan9373
22 - microchip,lan9374
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
[all …]
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
[all …]
H A Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-gmac
19 - const: allwinner,sun8i-v3s-emac
[all …]
H A Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
[all …]
H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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H A Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
H A Djh7110-starfive-visionfive-2-v1.2a.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
16 phy-mode = "rmii";
17 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
19 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
24 rx-internal-delay-ps = <1900>;
25 tx-internal-delay-ps = <1350>;
H A Djh7100-starfive-visionfive-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7100-common.dtsi"
12 compatible = "starfive,visionfive-v1", "starfive,jh7100";
14 gpio-restart {
15 compatible = "gpio-restart";
22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
27 * manual adjustment of the RX internal delay to work properly. The default
28 * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx8mp-skov-reva.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include <dt-bindings/leds/common.h>
26 compatible = "pwm-backlight";
27 pinctrl-0 = <&pinctrl_backlight>;
29 power-supply = <&reg_24v>;
30 enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
31 brightness-levels = <0 255>;
32 num-interpolated-steps = <17>;
33 default-brightness-level = <8>;
38 compatible = "gpio-leds";
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47094-asus-rt-ac88u.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "bcm47094-asus-rt-ac3100.dtsi"
11 compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
12 model = "ASUS RT-AC88U";
16 #nvmem-cell-cells = <1>;
22 mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
23 mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
24 reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
25 realtek,disable-leds;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am642-evm-icssg1-dualemac.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-pinctrl.h"
16 ethernet1 = "/icssg1-eth/ethernet-ports/port@1";
19 mdio-mux-2 {
20 compatible = "mdio-mux-multiplexer";
21 mux-controls = <&mdio_mux>;
22 mdio-parent-bus = <&icssg1_mdio>;
[all …]
/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-atl-x530.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 (x530/AT-GS980MX)
9 /dts-v1/;
10 #include "armada-385.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
15 model = "x530/AT-GS980MX";
19 stdout-path = "serial1:115200n8";
32 internal-regs {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins>;
[all …]
/linux/drivers/net/phy/
H A Dintel-xway.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
32 #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */
36 #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */
37 #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */
38 #define XWAY_MDIO_INIT_ADSC BIT(5) /* Link auto-downspeed detect */
47 #define ADVERTISED_MPD BIT(10) /* Multi-port device */
177 struct device *dev = &phydev->mdio.dev; in xway_gphy_rgmii_init()
185 /* Existing behavior was to use default pin strapping delay in rgmii in xway_gphy_rgmii_init()
186 * mode, but rgmii should have meant no delay. Warn existing users, in xway_gphy_rgmii_init()
[all …]
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dadi,adv7511.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
21 - adi,adv7511
22 - adi,adv7511w
23 - adi,adv7513
29 The ADV7511/11W/13 internal registers are split into four pages
37 reg-names:
40 needing a non-default address.
[all …]
/linux/drivers/mmc/host/
H A Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()
78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
79 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; in rockchip_mmc_get_phase()
81 if (priv->internal_phase) in rockchip_mmc_get_phase()
89 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_set_internal_phase()
93 u32 delay; in rockchip_mmc_set_internal_phase() local
[all …]
/linux/include/linux/platform_data/
H A Dpxa_sdhci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * PXA Platform - SDHCI platform data definitions
17 /* card always wired to host, like on-chip emmc */
19 /* Board design supports 8-bit data on SD/SDIO BUS */
23 * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
26 * mmp2: each step is roughly 100ps, 5bits width
30 * 1: choose feedback clk + delay value
31 * 2: choose internal clk
/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d3_ksz9477_evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 /dts-v1/;
9 model = "EVB-KSZ9477";
10 compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36",
14 stdout-path = &dbgu;
17 reg_3v3: regulator-3v3 {
18 compatible = "regulator-fixed";
19 regulator-name = "3v3";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
[all …]

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