Searched +full:imx8qxp +full:- +full:mipi +full:- +full:lvds +full:- +full:csr (Results 1 – 5 of 5) sorted by relevance
| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | fsl,imx8qxp-csr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 Registers(CSR) module represents a set of miscellaneous registers of a
17 use-case is for some other nodes to acquire a reference to the syscon node
18 by phandle, and the other typical use-case is that the operating system
19 should consider all subnodes of the CSR module as separate child devices.
23 pattern: "^syscon@[0-9a-f]+$"
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
24 Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
25 like I2C controller, PWM controller, MIPI DSI controller and Control and
26 Status Registers (CSR) module, are accessed through the bus.
35 - $ref: simple-pm-bus.yaml#
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| /linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | fsl,imx8qxp-pxl2dpi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pxl2dpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
14 interfaces the pixel link 36-bit data output and the DSI controller’s
15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
16 used in LVDS mode, to remap the pixel color codings between those modules.
19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
20 The CSR module, as a system controller, contains the PXL2DPI's configuration
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guido Günther <agx@sigxcpu.org>
13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
18 in either MIPI-DSI PHY mode or LVDS PHY mode.
23 - fsl,imx8mq-mipi-dphy
24 - fsl,imx8qxp-mipi-dphy
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| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
22 #include <dt-bindings/firmware/imx/rsrc.h>
24 /* Control and Status Registers(CSR) */
63 ((x) < 32) ? 0xe0 | ((x) - 16) : \
64 ((x) < 64) ? 0xc0 | ((x) - 32) : \
65 ((x) < 128) ? 0x80 | ((x) - 64) : \
66 ((x) - 128))
67 #define CN(x) (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
68 #define CO(x) ((CO_BUF) >> (8 - (x)) & 0x03)
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