/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8-ss-dma.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/dma/fsl-edma.h> 9 #include <dt-bindings/firmware/imx/rsrc.h> 11 dma_ipg_clk: clock-dma-ipg { 12 compatible = "fixed-clock"; 13 #clock-cells = <0>; 14 clock-frequency = <120000000>; 15 clock-output-names = "dma_ipg_clk"; [all …]
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H A D | imx8-ss-lsio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2020 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 10 lsio_bus_clk: clock-lsio-bus { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <100000000>; 14 clock-output-names = "lsio_bus_clk"; 18 compatible = "simple-bus"; [all …]
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H A D | imx8qm-ss-dma.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 8 uart4_lpcg: clock-controller@5a4a0000 { 9 compatible = "fsl,imx8qxp-lpcg"; 11 #clock-cells = <1>; 12 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>, 14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 15 clock-output-names = "uart4_lpcg_baud_clk", 17 power-domains = <&pd IMX_SC_R_UART_4>; 21 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; [all …]
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H A D | imx8-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 10 conn_axi_clk: clock-conn-axi { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <333333333>; 14 clock-output-names = "conn_axi_clk"; 17 conn_ahb_clk: clock-conn-ahb { [all …]
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H A D | imx8qxp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright 2017-2020 NXP 8 #include <dt-bindings/clock/imx8-clock.h> 9 #include <dt-bindings/clock/imx8-lpcg.h> 10 #include <dt-bindings/firmware/imx/rsrc.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/pinctrl/pads-imx8qxp.h> 15 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | imx8-ss-mipi1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 interrupt-parent = <&irqsteer_mipi1>; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 irqsteer_mipi1: interrupt-controller@57220000 { 15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 18 interrupt-controller; 19 interrupt-parent = <&gic>; 20 #interrupt-cells = <1>; [all …]
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H A D | imx8-ss-mipi0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 interrupt-parent = <&irqsteer_mipi0>; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 irqsteer_mipi0: interrupt-controller@56220000 { 15 compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer"; 18 interrupt-controller; 19 interrupt-parent = <&gic>; 20 #interrupt-cells = <1>; [all …]
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H A D | imx8-ss-lvds1.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 interrupt-parent = <&irqsteer_lvds1>; 10 #address-cells = <1>; 11 #size-cells = <1>; 14 irqsteer_lvds1: interrupt-controller@57240000 { 15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; 18 interrupt-controller; 19 interrupt-parent = <&gic>; 20 #interrupt-cells = <1>; [all …]
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H A D | imx8-ss-cm40.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 7 #include <dt-bindings/firmware/imx/rsrc.h> 9 cm40_ipg_clk: clock-cm40-ipg { 10 compatible = "fixed-clock"; 11 #clock-cells = <0>; 12 clock-frequency = <132000000>; 13 clock-output-names = "cm40_ipg_clk"; 17 compatible = "simple-bus"; 18 #address-cells = <1>; 19 #size-cells = <1>; [all …]
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H A D | imx8-ss-lvds0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only and MIT 8 compatible = "simple-bus"; 9 #address-cells = <1>; 10 #size-cells = <1>; 13 qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 { 14 compatible = "fsl,imx8qxp-lpcg"; 16 #clock-cells = <1>; 17 clock-output-names = "lvds0_lis_lpcg_ipg_clk"; 18 power-domains = <&pd IMX_SC_R_MIPI_1>; 21 qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c { [all …]
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H A D | imx8dxl-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 /delete-node/ &enet1_lpcg; 7 /delete-node/ &fec2; 10 conn_enet0_root_clk: clock-conn-enet0-root { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <250000000>; 14 clock-output-names = "conn_enet0_root_clk"; 17 clk_dummy: clock-dummy { 18 compatible = "fixed-clock"; [all …]
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H A D | imx8-ss-audio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-clock.h> 8 #include <dt-bindings/clock/imx8-lpcg.h> 9 #include <dt-bindings/dma/fsl-edma.h> 10 #include <dt-bindings/firmware/imx/rsrc.h> 12 audio_ipg_clk: clock-audio-ipg { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <120000000>; [all …]
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H A D | imx8dxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/clock/imx8-clock.h> 7 #include <dt-bindings/dma/fsl-edma.h> 8 #include <dt-bindings/clock/imx8-lpcg.h> 9 #include <dt-bindings/firmware/imx/rsrc.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/pinctrl/pads-imx8dxl.h> 14 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | imx8qxp-mek.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 6 /dts-v1/; 8 #include "imx8qxp.dtsi" 9 #include <dt-bindings/usb/pd.h> 13 compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; 16 stdout-path = &lpuart0; 24 reg_usdhc2_vmmc: usdhc2-vmmc { 25 compatible = "regulator-fixed"; 26 regulator-name = "SD1_SPWR"; 27 regulator-min-microvolt = <3000000>; [all …]
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H A D | imx8-ss-cm41.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 7 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-bindings/clock/imx8-lpcg.h> 10 cm41_ipg_clk: clock-cm41-ipg { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <132000000>; 14 clock-output-names = "cm41_ipg_clk"; 18 compatible = "simple-bus"; 19 #address-cells = <1>; [all …]
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H A D | imx8qxp-ai_ml.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 7 /dts-v1/; 9 #include "imx8qxp.dtsi" 13 compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp"; 22 stdout-path = &lpuart2; 31 compatible = "gpio-led [all...] |
/freebsd/sys/contrib/device-tree/Bindings/arm/freescale/ |
H A D | fsl,scu.txt | 2 -------------------------------------------------------------------- 4 The System Controller Firmware (SCFW) is a low-level system function 5 which runs on a dedicated Cortex-M core to provide power, clock, and 9 The AP communicates with the SC using a multi-ported MU module found 22 ------------------- 23 - compatible: should be "fsl,imx-scu". 24 - mbox-names: should include "tx0", "tx1", "tx2", "tx3", 27 - mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for 31 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need 63 Client nodes are maintained as children of the relevant IMX-SCU device node. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | fsl,scu-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: i.MX SCU Client Device Node - Clock Controller Based on SCU Message Protocol 10 - Abel Vesa <abel.vesa@nxp.com> 13 Client nodes are maintained as children of the relevant IMX-SCU device node. 15 (Documentation/devicetree/bindings/clock/clock-bindings.txt) 18 include/dt-bindings/clock/imx8qxp-clock.h 23 - enum: [all …]
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
H A D | nxp,imx8qxp-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP IMX8QXP ADC 10 - Cai Huoqing <caihuoqing@baidu.com> 13 Supports the ADC found on the IMX8QXP SoC. 17 const: nxp,imx8qxp-adc 28 clock-names: 30 - const: per [all …]
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/freebsd/sys/contrib/device-tree/Bindings/firmware/ |
H A D | fsl,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dong Aisheng <aisheng.dong@nxp.com> 13 The System Controller Firmware (SCFW) is a low-level system function 14 which runs on a dedicated Cortex-M core to provide power, clock, and 17 The AP communicates with the SC using a multi-ported MU module found 26 const: fsl,imx-scu 28 clock-controller: 31 $ref: /schemas/clock/fsl,scu-clk.yaml [all …]
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/freebsd/sys/contrib/device-tree/Bindings/mfd/ |
H A D | fsl,imx8qxp-csr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 17 use-case is for some other nodes to acquire a reference to the syscon node 18 by phandle, and the other typical use-case is that the operating system 23 pattern: "^syscon@[0-9a-f]+$" 27 - enum: 28 - fsl,imx8qxp-mipi-lvds-csr [all …]
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/freebsd/sys/contrib/device-tree/Bindings/bus/ |
H A D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp [all...] |
/freebsd/sys/contrib/device-tree/Bindings/sound/ |
H A D | fsl,imx-asrc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/fsl,imx-asrc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 17 - Shawn Guo <shawnguo@kernel.org> 18 - Sascha Hauer <s.hauer@pengutronix.de> 23 - enum: 24 - fsl,imx35-asrc 25 - fsl,imx53-asrc 26 - fsl,imx8qm-asrc [all …]
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/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | mixel,mipi-dsi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Guido Günther <agx@sigxcpu.org> 13 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the 14 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the 18 in either MIPI-DSI PHY mode or LVDS PHY mode. 23 - fsl,imx8mq-mipi-dphy 24 - fsl,imx8qxp-mipi-dphy [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
H A D | fsl,imx8qxp-ldb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 41 - fsl,imx8qm-ldb 42 - fsl,imx8qxp-ldb 44 "#address-cells": 47 "#size-cells": 52 - description: pixel clock [all …]
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