Home
last modified time | relevance | path

Searched +full:imx8mp +full:- +full:power (Results 1 – 25 of 53) sorted by relevance

123

/linux/Documentation/devicetree/bindings/dsp/
H A Dfsl,dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
11 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 advanced pre- and post- audio processing.
20 - fsl,imx8qxp-dsp
21 - fsl,imx8qm-dsp
22 - fsl,imx8mp-dsp
23 - fsl,imx8ulp-dsp
[all …]
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
20 - const: fsl,imx8mp-hsio-blk-ctrl
21 - const: syscon
[all …]
H A Dfsl,imx8mp-hdmi-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HDMI blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display pipeline
20 - const: fsl,imx8mp-hdmi-blk-ctrl
21 - const: syscon
[all …]
H A Dfsl,imx8mp-media-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
14 providing access to the NoC and ensuring proper power sequencing of the
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#address-cells':
[all …]
H A Dfsl,imx8mm-vpu-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
20 - const: fsl,imx8mm-vpu-blk-ctrl
21 - const: syscon
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
35 - description: The AHB clock
[all …]
/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx8mp-hdmi-pvi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
18 const: fsl,imx8mp-hdmi-pvi
26 power-domains:
42 - port@0
43 - port@1
46 - compatible
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8mp-aipstz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8mp-aipstz.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
20 const: fsl,imx8mp-aipstz
25 power-domains:
28 "#address-cells":
31 "#size-cells":
34 "#access-controller-cells":
[all …]
/linux/Documentation/devicetree/bindings/power/
H A Dfsl,imx-gpcv2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX General Power Controller v2
10 - Andrey Smirnov <andrew.smirnov@gmail.com>
13 The i.MX7S/D General Power Control (GPC) block contains Power Gating
14 Control (PGC) for various power domains.
16 Power domains contained within GPC node are generic power domain
18 Documentation/devicetree/bindings/power/power-domain.yaml, which are
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dfsl,lcdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Stefan Agner <stefan@agner.ch>
19 - enum:
20 - fsl,imx23-lcdif
21 - fsl,imx28-lcdif
22 - fsl,imx6sx-lcdif
23 - fsl,imx8mp-lcdif
[all …]
/linux/drivers/usb/dwc3/
H A Ddwc3-imx8mp.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
45 #define USB_CTRL0_PORTPWR_EN BIT(12) /* 1 - PPC enabled (default) */
46 #define USB_CTRL0_USB3_FIXED BIT(22) /* 1 - USB3 permanent attached */
47 #define USB_CTRL0_USB2_FIXED BIT(23) /* 1 - USB2 permanent attached */
49 #define USB_CTRL1_OC_POLARITY BIT(16) /* 0 - HIGH / 1 - LOW */
50 #define USB_CTRL1_PWR_POLARITY BIT(17) /* 0 - HIGH / 1 - LOW */
66 struct device *dev = dwc3_imx->dev; in imx8mp_configure_glue()
69 if (!dwc3_imx->glue_base) in imx8mp_configure_glue()
72 value = readl(dwc3_imx->glue_base + USB_CTRL0); in imx8mp_configure_glue()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dfsl,aud2htx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
14 const: fsl,imx8mp-aud2htx
24 - description: Peripheral clock
26 clock-names:
28 - const: bus
32 - description: DMA controller phandle and request line for TX
34 dma-names:
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-skov-revb-mi1010ait-1cp1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 /dts-v1/;
5 #include "imx8mp-skov-reva.dtsi"
8 model = "SKOV IMX8MP CPU revB - MI1010AIT-1CP1";
9 compatible = "skov,imx8mp-skov-revb-mi1010ait-1cp1", "fsl,imx8mp";
12 compatible = "multi-inno,mi1010ait-1cp";
14 power-supply = <&reg_tft_vcom>;
18 remote-endpoint = <&ldb_lvds_ch0>;
29 clock-frequency = <100000>;
33 compatible = "edt,edt-ft5406";
[all …]
H A Dimx8mp-skov-revc-tian-g07017.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 /dts-v1/;
5 #include "imx8mp-skov-reva.dtsi"
8 model = "SKOV IMX8MP CPU revC - TIAN G07017";
9 compatible = "skov,imx8mp-skov-revc-tian-g07017", "fsl,imx8mp";
12 compatible = "topland,tian-g07017-01";
14 power-supply = <&reg_tft_vcom>;
18 remote-endpoint = <&ldb_lvds_ch0>;
29 clock-frequency = <100000>;
33 compatible = "edt,edt-ft5506";
[all …]
H A Dimx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/imx8mp-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
10 #include "imx8mp-pinfunc.h"
12 /dts-v1/;
16 model = "GOcontroll Moduline Display with BOE av101hdt-a10 display";
19 compatible = "boe,av101hdt-a10";
20 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
21 pinctrl-0 = <&pinctrl_panel>;
22 pinctrl-names = "default";
[all …]
H A Dimx8mp-libra-rdk-fpsc.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/leds/leds-pca9532.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include "imx8mp-phycore-fpsc.dtsi"
14 compatible = "phytec,imx8mp-libra-rdk-fpsc",
15 "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";
19 compatible = "pwm-backlight";
20 pinctrl-0 = <&pinctrl_lvds0>;
[all …]
H A Dimx8mp-dhcom-pdk3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * DHCOM iMX8MP variant:
6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * PDK3 PCB number: 669-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/phy/phy-imx8-pcie.h>
15 #include "imx8mp-dhcom-som.dtsi"
19 compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",
[all …]
H A Dimx8mp-venice-gw74xx-rpidsi.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
13 compatible = "powertip,ph800480t013-idf02";
14 power-supply = <&attiny>;
19 remote-endpoint = <&bridge_out>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "raspberrypi,7inch-touchscreen-panel-regulator";
40 samsung,burst-clock-frequency = <891000000>;
[all …]
H A Dimx8mp-phyboard-pollux-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include <dt-bindings/leds/leds-pca9532.h>
11 #include <dt-bindings/pwm/pwm.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include "imx8mp-phycore-som.dtsi"
16 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
17 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
18 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dfsl,imx-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Co-Processor
10 This binding provides support for ARM Cortex M4 Co-processor found on some NXP iMX SoCs.
13 - Peng Fan <peng.fan@nxp.com>
18 - fsl,imx6sx-cm4
19 - fsl,imx7d-cm4
20 - fsl,imx7ulp-cm4
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,irqsteer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
15 - const: fsl,imx-irqsteer
16 - items:
17 - enum:
18 - fsl,imx8m-irqsteer
19 - fsl,imx8mp-irqsteer
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
[all …]
H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - enum:
16 - fsl,imx8mq-usb-phy
17 - fsl,imx8mp-usb-phy
18 - items:
19 - const: fsl,imx95-usb-phy
[all …]
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8mp-hdmi-tx.c1 // SPDX-License-Identifier: GPL-2.0+
28 if (mode->clock < 13500) in imx8mp_hdmi_mode_valid()
31 if (mode->clock > 297000) in imx8mp_hdmi_mode_valid()
34 round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000); in imx8mp_hdmi_mode_valid()
35 /* imx8mp's pixel clock generator (fsl-samsung-hdmi) cannot generate in imx8mp_hdmi_mode_valid()
39 * 0.5% = 5/1000 tolerance (mode->clock is 1/1000) in imx8mp_hdmi_mode_valid()
41 if (abs(round_rate - mode->clock * 1000) > mode->clock * 5) in imx8mp_hdmi_mode_valid()
44 /* We don't support double-clocked and Interlaced modes */ in imx8mp_hdmi_mode_valid()
45 if ((mode->flags & DRM_MODE_FLAG_DBLCLK) || in imx8mp_hdmi_mode_valid()
46 (mode->flags & DRM_MODE_FLAG_INTERLACE)) in imx8mp_hdmi_mode_valid()
[all …]
/linux/Documentation/devicetree/bindings/power/reset/
H A Dtoradex,smarc-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/toradex,smarc-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
11 - Francesco Dolcini <francesco.dolcini@toradex.com>
15 primarily to manage power and reset functionalities.
18 - Reads the SMARC POWER_BTN# and RESET_IN# signals and controls the PMIC accordingly.
19 - Controls the SoC boot mode signals based on the SMARC BOOT_SEL# and FORCE_RECOV# inputs.
20 - Manages the CARRIER_STDBY# signal in response to relevant SoC signals.
[all …]

123