/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8qxp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright 2017-2020 NXP 8 #include <dt-bindings/clock/imx8-clock.h> 9 #include <dt-binding [all...] |
H A D | imx8dxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/clock/imx8-clock.h> 7 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-binding [all...] |
H A D | imx8qm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 #include <dt-binding [all...] |
H A D | imx8-ss-audio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 10 audio_ipg_clk: clock [all...] |
H A D | imx8mm-venice-gw71xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 16 led-controlle [all...] |
H A D | imx8mp-venice-gw7905.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 led-controller { 12 compatible = "gpio-leds"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpio_leds>; 16 led-0 { 20 default-state = "on"; [all …]
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H A D | imx8mp-dhcom-pdk2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN [all...] |
H A D | imx8qm-apalis.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 6 #include "imx8qm-apalis-v1.1.dtsi" 10 compatible = "toradex,apalis-imx8", 24 phy-mod [all...] |
H A D | imx8mm-venice-gw72xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 17 led-controlle [all...] |
H A D | imx8-ss-conn.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 10 conn_axi_clk: clock [all...] |
H A D | imx8mp-dhcom-pdk3.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN [all...] |
H A D | imx8mm-phyboard-polis-rdk.dts | 1 // SPDX-License-Identifier: GPL-2.0 7 /dts-v1/; 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/phy/phy-imx8 [all...] |
H A D | imx8mm-beacon-baseboard.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 #include <dt-bindings/phy/phy-imx8-pcie.h> 10 dmic_codec: dmic-codec { 11 compatible = "dmic-codec"; 12 num-channel [all...] |
H A D | imx8-ss-lsio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2020 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 10 lsio_bus_clk: clock [all...] |
H A D | imx8mm-venice-gw73xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 17 led-controlle [all...] |
/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | imx8qxp-lpcg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock 10 - Aisheng Dong <aisheng.dong@nxp.com> 13 The Low-Power Clock Gate (LPCG) modules contain a local programming 14 model to control the clock gates for the peripherals. An LPCG module 17 This level of clock gating is provided after the clocks are generated 18 by the SCU resources and clock controls. Thus even if the clock is [all …]
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/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | fsl,imx8-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Richard Zhu <hongxing.zhu@nxp.com> 13 "#phy-cells": 18 - fsl,imx8mm-pcie-phy 19 - fsl,imx8mp-pcie-phy 27 clock-names: 29 - const: ref [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | imx-dwmac.txt | 1 IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP. 9 - compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer 10 and "snps,dwmac-5.10a" to select IP version. 11 - clocks: Must contain a phandle for each entry in clock-names. 12 - clock-names: Should be "stmmaceth" for the host clock. 13 Should be "pclk" for the MAC apb clock. 14 Should be "ptp_ref" for the MAC timer clock. 15 Should be "tx" for the MAC RGMII TX clock: 16 Should be "mem" for EQOS MEM clock. 17 - "mem" clock is required for imx8dxl platform. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/usb/ |
H A D | fsl,imx8qm-cdns3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Frank Li <Frank.Li@nxp.com> 15 const: fsl,imx8qm-usb3 19 - description: Register set for iMX USB3 Platform Control 21 "#address-cells": 24 "#size-cells": 31 - description: Standby clock. Used during ultra low power states. [all …]
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/freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
H A D | fsl,imx8qxp-pixel-combiner.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 23 - fsl,imx8qm-pixel-combiner 24 - fsl,imx8qxp-pixel-combiner 26 "#address-cells": 29 "#size-cells": 38 clock-names: [all …]
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/freebsd/sys/contrib/device-tree/Bindings/media/ |
H A D | nxp,imx8-isi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx8 [all...] |
/freebsd/sys/contrib/device-tree/Bindings/mfd/ |
H A D | fsl,imx8qxp-csr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 17 use-case is for some other nodes to acquire a reference to the syscon node 18 by phandle, and the other typical use-case is that the operating system 23 pattern: "^syscon@[0-9a-f]+$" 27 - enum: 28 - fsl,imx8qxp-mipi-lvds-csr [all …]
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/freebsd/sys/contrib/device-tree/Bindings/dsp/ |
H A D | fsl,dsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daniel Baluta <daniel.baluta@nxp.com> 11 - Shengjiu Wang <shengjiu.wang@nxp.com> 15 advanced pre- and post- audio processing. 20 - fsl,imx8qxp-dsp 21 - fsl,imx8qm-dsp 22 - fsl,imx8mp-dsp 23 - fsl,imx8ulp-dsp [all …]
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/freebsd/sys/contrib/device-tree/Bindings/bus/ |
H A D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixe [all...] |
/freebsd/sys/contrib/device-tree/Bindings/firmware/ |
H A D | fsl,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dong Aisheng <aisheng.dong@nxp.com> 13 The System Controller Firmware (SCFW) is a low-level system function 14 which runs on a dedicated Cortex-M core to provide power, clock, and 17 The AP communicates with the SC using a multi-ported MU module found 26 const: fsl,imx-scu 28 clock-controller: 30 Clock controller node that provides the clocks controlled by the SCU [all …]
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