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Searched +full:imx6q +full:- +full:mmdc (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dmmdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/mmdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Multi Mode DDR controller (MMDC)
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
17 - const: fsl,imx6q-mmdc
18 - items:
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qp.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 #include "imx6q.dtsi"
10 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
19 compatible = "mmio-sram";
22 #address-cells = <1>;
23 #size-cells = <1>;
29 compatible = "fsl,imx6qp-pre";
33 clock-names = "axi";
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H A Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
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H A Dimx6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #include <dt-bindings/clock/imx6ul-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include "imx6ul-pinfunc.h"
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
57 #address-cells = <1>;
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/linux/arch/arm/mach-imx/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y := cpu.o system.o irq-common.o
4 obj-$(CONFIG_SOC_IMX25) += cpu-imx25.o mach-imx25.o pm-imx25.o
6 obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o mach-imx27.o
8 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o mach-imx31.o
9 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o mach-imx35.o
11 imx5-pm-$(CONFIG_PM) += pm-imx5.o
12 obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o $(imx5-pm-y)
14 obj-$(CONFIG_MXC_TZIC) += tzic.o
15 obj-$(CONFIG_MXC_AVIC) += avic.o
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H A Dsuspend-imx6.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/asm-offsets.h>
9 #include <asm/hardware/cache-l2x0.h>
12 .arch armv7-a
38 * which defined in arch/arm/mach-imx/pm-imx6q.c, this
94 /* restore MMDC IO */
135 /* let DDR out of self-refresh */
169 * as we will access them after MMDC IO floated.
190 * put DDR explicitly into self-refresh and
197 /* make the DDR explicitly enter self-refresh. */
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/linux/drivers/clk/imx/
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
135 return of_machine_is_compatible("fsl,imx6q"); in clk_on_imx6q()
154 return -ENOENT; in ldb_di_sel_by_clock_id()
165 return -ENOENT; in ldb_di_sel_by_clock_id()
177 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents", in of_assigned_ldb_sels()
178 "#clock-cells"); in of_assigned_ldb_sels()
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H A Dclk-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
138 clk_hw_data->num = IMX6UL_CLK_END; in imx6ul_clocks_init()
139 hws = clk_hw_data->hws; in imx6ul_clocks_init()
150 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); in imx6ul_clocks_init()
180 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
181 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
182 clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk); in imx6ul_clocks_init()
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H A Dclk-imx6sx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6sx-clock.h>
10 #include <linux/clk-provider.h>
131 clk_hw_data->num = IMX6SX_CLK_CLK_END; in imx6sx_clocks_init()
132 hws = clk_hw_data->hws; in imx6sx_clocks_init()
147 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop"); in imx6sx_clocks_init()
178 clk_set_parent(hws[IMX6SX_PLL1_BYPASS]->clk, hws[IMX6SX_CLK_PLL1]->clk); in imx6sx_clocks_init()
179 clk_set_parent(hws[IMX6SX_PLL2_BYPASS]->clk, hws[IMX6SX_CLK_PLL2]->clk); in imx6sx_clocks_init()
180 clk_set_parent(hws[IMX6SX_PLL3_BYPASS]->clk, hws[IMX6SX_CLK_PLL3]->clk); in imx6sx_clocks_init()
181 clk_set_parent(hws[IMX6SX_PLL4_BYPASS]->clk, hws[IMX6SX_CLK_PLL4]->clk); in imx6sx_clocks_init()
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