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/linux/Documentation/devicetree/bindings/clock/
H A Dimx1-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx1-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Shiyan <shc_work@mail.ru>
14 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx1-clock.h
19 const: fsl,imx1-ccm
24 '#clock-cells':
28 - compatible
29 - reg
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx1.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/imx1-clock.h>
28 static void __iomem *ccm __initdata;
29 #define CCM_CSCR (ccm + 0x0000)
30 #define CCM_MPCTL0 (ccm + 0x0004)
31 #define CCM_SPCTL0 (ccm + 0x000c)
32 #define CCM_PCDR (ccm + 0x0020)
33 #define SCM_GCCR (ccm + 0x0810)
37 ccm = of_iomap(np, 0); in mx1_clocks_init_dt()
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx1.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx1-pinfunc.h"
7 #include <dt-bindings/clock/imx1-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
34 aitc: aitc-interrupt-controller@223000 {
35 compatible = "fsl,imx1-aitc", "fsl,avic";
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H A Dimx35.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include "imx35-pinfunc.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1136jf-s";
48 avic: avic-interrupt-controller@68000000 {
49 compatible = "fsl,imx35-avic", "fsl,avic";
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/linux/arch/m68k/coldfire/
H A Dm5441x.c1 // SPDX-License-Identifier: GPL-2.0
3 * m5441x.c -- support for Coldfire m5441x processors
24 DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
30 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
31 DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK);
49 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
50 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
51 DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
56 DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
57 DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
[all …]