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/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_tee.c63 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_tee_io_message() local
70 * The binding of the component is asynchronous from i915 probe, so we in intel_pxp_tee_io_message()
81 drm_err(&i915->drm, "Failed to send PXP TEE message\n"); in intel_pxp_tee_io_message()
88 drm_err(&i915->drm, "Failed to receive PXP TEE message\n"); in intel_pxp_tee_io_message()
93 drm_err(&i915->drm, in intel_pxp_tee_io_message()
115 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_tee_stream_message() local
140 drm_err(&i915->drm, "Failed to send PXP TEE gsc command\n"); in intel_pxp_tee_stream_message()
151 * @i915_kdev: pointer to i915 kernel device
162 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); in i915_pxp_tee_component_bind() local
163 struct intel_pxp *pxp = i915->pxp; in i915_pxp_tee_component_bind()
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H A Dintel_pxp_gsccs.c60 struct drm_i915_private *i915 = gt->i915; in gsccs_send_message() local
117 drm_err(&i915->drm, "failed to send gsc PXP msg (%d)\n", ret); in gsccs_send_message()
123 drm_err(&i915->drm, "gsc PXP reply with invalid validity marker\n"); in gsccs_send_message()
128 drm_dbg(&i915->drm, "gsc PXP reply status has error = 0x%08x\n", in gsccs_send_message()
134 drm_dbg(&i915->drm, "gsc PXP reply is busy\n"); in gsccs_send_message()
148 drm_warn(&i915->drm, "caller with insufficient PXP reply size %u (%zu)\n", in gsccs_send_message()
211 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_gsccs_create_session() local
228 drm_err(&i915->drm, "Failed to init session %d, ret=[%d]\n", arb_session_id, ret); in intel_pxp_gsccs_create_session()
231 drm_info_once(&i915->drm, in intel_pxp_gsccs_create_session()
236 drm_dbg(&i915->drm, "PXP init-session-%d failed 0x%08x:%st:\n", in intel_pxp_gsccs_create_session()
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_region_lmem.c32 _resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size) in _resize_bar() argument
34 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in _resize_bar()
42 drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n", in _resize_bar()
47 drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); in _resize_bar()
50 static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size) in i915_resize_lmem_bar() argument
52 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in i915_resize_lmem_bar()
63 if (i915->params.lmem_bar_size) { in i915_resize_lmem_bar()
66 rebar_size = i915->params.lmem_bar_size * in i915_resize_lmem_bar()
77 drm_info(&i915->drm, in i915_resize_lmem_bar()
102 drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n"); in i915_resize_lmem_bar()
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H A Dintel_wopcm.c81 struct drm_i915_private *i915 = gt->i915; in intel_wopcm_init_early() local
83 if (!HAS_GT_UC(i915)) in intel_wopcm_init_early()
86 if (GRAPHICS_VER(i915) >= 11) in intel_wopcm_init_early()
91 drm_dbg(&i915->drm, "WOPCM: %uK\n", wopcm->size / 1024); in intel_wopcm_init_early()
94 static u32 context_reserved_size(struct drm_i915_private *i915) in context_reserved_size() argument
96 if (IS_GEN9_LP(i915)) in context_reserved_size()
98 else if (GRAPHICS_VER(i915) >= 11) in context_reserved_size()
104 static bool gen9_check_dword_gap(struct drm_i915_private *i915, in gen9_check_dword_gap() argument
117 drm_err(&i915->drm, in gen9_check_dword_gap()
127 static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915, in gen9_check_huc_fw_fits() argument
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H A Dintel_engine_user.c17 intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance) in intel_engine_lookup_user() argument
19 struct rb_node *p = i915->uabi_engines.rb_node; in intel_engine_lookup_user()
41 llist_add(&engine->uabi_llist, &engine->i915->uabi_engines_llist); in intel_engine_add_user()
76 static struct llist_node *get_engines(struct drm_i915_private *i915) in get_engines() argument
78 return llist_del_all(&i915->uabi_engines_llist); in get_engines()
81 static void sort_engines(struct drm_i915_private *i915, in sort_engines() argument
86 llist_for_each_safe(pos, next, get_engines(i915)) { in sort_engines()
94 static void set_scheduler_caps(struct drm_i915_private *i915) in set_scheduler_caps() argument
111 for_each_uabi_engine(engine, i915) { /* all engines must agree! */ in set_scheduler_caps()
132 i915->caps.scheduler = enabled & ~disabled; in set_scheduler_caps()
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H A Dintel_gsc.c49 obj = i915_gem_object_create_lmem(gt->i915, size, in gsc_ext_om_alloc()
128 static void gsc_destroy_one(struct drm_i915_private *i915, in gsc_destroy_one() argument
152 static void gsc_init_one(struct drm_i915_private *i915, struct intel_gsc *gsc, in gsc_init_one() argument
155 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in gsc_init_one()
169 drm_dbg(&i915->drm, "Not initializing gsc for remote tiles\n"); in gsc_init_one()
173 if (intf_id == 0 && !HAS_HECI_PXP(i915)) in gsc_init_one()
176 if (IS_DG1(i915)) { in gsc_init_one()
178 } else if (IS_DG2(i915)) { in gsc_init_one()
181 drm_warn_once(&i915->drm, "Unknown platform\n"); in gsc_init_one()
186 drm_warn_once(&i915->drm, "HECI%d is not implemented!\n", intf_id + 1); in gsc_init_one()
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H A Dintel_gt_print.h14 drm_err(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
17 drm_warn(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
20 drm_warn_once(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
23 drm_notice(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
26 drm_info(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
29 drm_dbg(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
32 drm_err_ratelimited(&(_gt)->i915->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
35 dev_notice_ratelimited((_gt)->i915->drm.dev, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
46 drm_WARN(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
49 drm_WARN_ONCE(&(_gt)->i915->drm, _condition, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__)
/linux/drivers/gpu/drm/i915/
H A Dintel_step.c135 static u8 gmd_to_intel_step(struct drm_i915_private *i915, in gmd_to_intel_step() argument
141 drm_dbg(&i915->drm, "Using future steppings\n"); in gmd_to_intel_step()
148 void intel_step_init(struct drm_i915_private *i915) in intel_step_init() argument
152 int revid = INTEL_REVID(i915); in intel_step_init()
155 if (HAS_GMD_ID(i915)) { in intel_step_init()
156 step.graphics_step = gmd_to_intel_step(i915, in intel_step_init()
157 &RUNTIME_INFO(i915)->graphics.ip); in intel_step_init()
158 step.media_step = gmd_to_intel_step(i915, in intel_step_init()
159 &RUNTIME_INFO(i915)->media.ip); in intel_step_init()
161 RUNTIME_INFO(i915)->step = step; in intel_step_init()
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H A Dintel_device_info.c229 static void intel_device_info_subplatform_init(struct drm_i915_private *i915) in intel_device_info_subplatform_init() argument
231 const struct intel_device_info *info = INTEL_INFO(i915); in intel_device_info_subplatform_init()
232 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); in intel_device_info_subplatform_init()
235 u16 devid = INTEL_DEVID(i915); in intel_device_info_subplatform_init()
239 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); in intel_device_info_subplatform_init()
248 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { in intel_device_info_subplatform_init()
294 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; in intel_device_info_subplatform_init()
297 static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip) in ip_ver_read() argument
299 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in ip_ver_read()
306 if (drm_WARN_ON(&i915->drm, !addr)) in ip_ver_read()
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H A DMakefile12 # Support compiling the display code separately for both i915 and xe
13 # drivers. Define I915 when building i915.
21 i915-y += \
52 i915-y += \
58 i915-y += \
66 i915-$(CONFIG_COMPAT) += \
68 i915-$(CONFIG_DEBUG_FS) += \
71 i915-$(CONFIG_PERF_EVENTS) += \
138 i915-y += $(gt-y)
168 i915-y += \
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H A Di915_pmu.c151 struct drm_i915_private *i915 = pmu_to_i915(pmu); in pmu_needs_timer() local
171 if (i915->caps.scheduler & I915_SCHEDULER_CAP_ENGINE_BUSY_STATS) in pmu_needs_timer()
182 struct drm_i915_private *i915 = gt->i915; in __get_rc6() local
187 if (HAS_RC6p(i915)) in __get_rc6()
190 if (HAS_RC6pp(i915)) in __get_rc6()
220 struct drm_i915_private *i915 = gt->i915; in get_rc6() local
222 struct i915_pmu *pmu = &i915->pmu; in get_rc6()
261 struct drm_i915_private *i915 = pmu_to_i915(pmu); in init_rc6() local
265 for_each_gt(gt, i915, i) { in init_rc6()
281 struct i915_pmu *pmu = &gt->i915->pmu; in park_rc6()
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H A Di915_perf.c29 * DOC: i915 Perf Overview
35 * This i915 perf interface enables userspace to configure and open a file
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
51 * DOC: i915 Perf History and Comparison with Core Perf
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
95 * how userspace will sometimes need to combine i915 perf OA metrics with
103 * better suited to exposing i915 metrics these were the main pain points we
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H A Di915_hwmon.c300 static int hwm_pcode_read_i1(struct drm_i915_private *i915, u32 *uval) in hwm_pcode_read_i1() argument
303 if (IS_DG1(i915) || IS_DG2(i915)) in hwm_pcode_read_i1()
306 return snb_pcode_read_p(&i915->uncore, PCODE_POWER_SETUP, in hwm_pcode_read_i1()
310 static int hwm_pcode_write_i1(struct drm_i915_private *i915, u32 uval) in hwm_pcode_write_i1() argument
312 return snb_pcode_write_p(&i915->uncore, PCODE_POWER_SETUP, in hwm_pcode_write_i1()
350 struct drm_i915_private *i915 = ddat->uncore->i915; in hwm_in_is_visible() local
354 return IS_DG1(i915) || IS_DG2(i915) ? 0444 : 0; in hwm_in_is_visible()
382 struct drm_i915_private *i915 = ddat->uncore->i915; in hwm_power_is_visible() local
392 return (hwm_pcode_read_i1(i915, &uval) || in hwm_power_is_visible()
515 ret = hwm_pcode_read_i1(ddat->uncore->i915, &uval); in hwm_power_read()
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H A Di915_sysfs.c47 static int l3_access_valid(struct drm_i915_private *i915, loff_t offset) in l3_access_valid() argument
49 if (!HAS_L3_DPF(i915)) in l3_access_valid()
67 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); in i915_l3_read() local
71 ret = l3_access_valid(i915, offset); in i915_l3_read()
79 spin_lock(&i915->gem.contexts.lock); in i915_l3_read()
80 if (i915->l3_parity.remap_info[slice]) in i915_l3_read()
82 i915->l3_parity.remap_info[slice] + offset / sizeof(u32), in i915_l3_read()
84 spin_unlock(&i915->gem.contexts.lock); in i915_l3_read()
95 struct drm_i915_private *i915 = kdev_minor_to_i915(kdev); in i915_l3_write() local
101 ret = l3_access_valid(i915, offset); in i915_l3_write()
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H A Di915_hwmon.h16 void i915_hwmon_register(struct drm_i915_private *i915);
17 void i915_hwmon_unregister(struct drm_i915_private *i915);
18 void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old);
19 void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old);
21 static inline void i915_hwmon_register(struct drm_i915_private *i915) { }; in i915_hwmon_register() argument
22 static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { }; in i915_hwmon_unregister() argument
23 static inline void i915_hwmon_power_max_disable(struct drm_i915_private *i915, bool *old) { }; in i915_hwmon_power_max_disable() argument
24 static inline void i915_hwmon_power_max_restore(struct drm_i915_private *i915, bool old) { }; in i915_hwmon_power_max_restore() argument
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-i915-hwmon1 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/in0_input
7 Only supported for particular Intel i915 graphics platforms.
9 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_max
21 Only supported for particular Intel i915 graphics platforms.
23 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_rated_max
29 Only supported for particular Intel i915 graphics platforms.
31 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_max_interval
38 Only supported for particular Intel i915 graphics platforms.
40 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_crit
51 Only supported for particular Intel i915 graphics platforms.
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/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_dmabuf.c20 struct drm_i915_private *i915 = arg; in igt_dmabuf_export() local
24 obj = i915_gem_object_create_shmem(i915, PAGE_SIZE); in igt_dmabuf_export()
42 struct drm_i915_private *i915 = arg; in igt_dmabuf_import_self() local
48 obj = i915_gem_object_create_shmem(i915, PAGE_SIZE); in igt_dmabuf_import_self()
60 import = i915_gem_prime_import(&i915->drm, dmabuf); in igt_dmabuf_import_self()
95 struct drm_i915_private *i915 = arg; in igt_dmabuf_import_same_driver_lmem() local
96 struct intel_memory_region *lmem = i915->mm.regions[INTEL_REGION_LMEM_0]; in igt_dmabuf_import_same_driver_lmem()
107 obj = __i915_gem_object_create_user(i915, PAGE_SIZE, &lmem, 1); in igt_dmabuf_import_same_driver_lmem()
127 import = i915_gem_prime_import(&i915->drm, dmabuf); in igt_dmabuf_import_same_driver_lmem()
148 static int verify_access(struct drm_i915_private *i915, in verify_access() argument
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H A Di915_gem_object.c15 struct drm_i915_private *i915 = arg; in igt_gem_object() local
21 obj = i915_gem_object_create_shmem(i915, PAGE_SIZE); in igt_gem_object()
37 struct drm_i915_private *i915 = arg; in igt_gem_huge() local
44 obj = huge_gem_object(i915, in igt_gem_huge()
46 to_gt(i915)->ggtt->vm.total + PAGE_SIZE); in igt_gem_huge()
79 struct drm_i915_private *i915; in i915_gem_object_mock_selftests() local
82 i915 = mock_gem_device(); in i915_gem_object_mock_selftests()
83 if (!i915) in i915_gem_object_mock_selftests()
86 err = i915_subtests(tests, i915); in i915_gem_object_mock_selftests()
88 mock_destroy_device(i915); in i915_gem_object_mock_selftests()
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/linux/drivers/gpu/drm/i915/selftests/
H A Digt_live_test.c16 struct drm_i915_private *i915, in igt_live_test_begin() argument
26 t->i915 = i915; in igt_live_test_begin()
30 for_each_gt(gt, i915, i) { in igt_live_test_begin()
41 i915_reset_engine_count(&i915->gpu_error, in igt_live_test_begin()
45 t->reset_global = i915_reset_count(&i915->gpu_error); in igt_live_test_begin()
52 struct drm_i915_private *i915 = t->i915; in igt_live_test_end() local
58 if (igt_flush_test(i915)) in igt_live_test_end()
61 if (t->reset_global != i915_reset_count(&i915->gpu_error)) { in igt_live_test_end()
64 i915_reset_count(&i915->gpu_error) - t->reset_global); in igt_live_test_end()
68 for_each_gt(gt, i915, i) { in igt_live_test_end()
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H A Di915_active.c63 static struct live_active *__live_alloc(struct drm_i915_private *i915) in __live_alloc() argument
78 __live_active_setup(struct drm_i915_private *i915) in __live_active_setup() argument
86 active = __live_alloc(i915); in __live_active_setup()
100 for_each_uabi_engine(engine, i915) { in __live_active_setup()
147 struct drm_i915_private *i915 = arg; in live_active_wait() local
153 active = __live_active_setup(i915); in live_active_wait()
159 struct drm_printer p = drm_err_printer(&i915->drm, __func__); in live_active_wait()
169 if (igt_flush_test(i915)) in live_active_wait()
177 struct drm_i915_private *i915 = arg; in live_active_retire() local
183 active = __live_active_setup(i915); in live_active_retire()
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/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_stolen.h17 int i915_gem_stolen_insert_node(struct drm_i915_private *i915,
20 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *i915,
24 void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
27 i915_gem_stolen_smem_setup(struct drm_i915_private *i915, u16 type,
30 i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
34 i915_gem_object_create_stolen(struct drm_i915_private *i915,
41 bool i915_gem_stolen_initialized(const struct drm_i915_private *i915);
42 u64 i915_gem_stolen_area_address(const struct drm_i915_private *i915);
43 u64 i915_gem_stolen_area_size(const struct drm_i915_private *i915);
45 u64 i915_gem_stolen_node_address(const struct drm_i915_private *i915,
H A Di915_gem_shmem.c63 int shmem_sg_alloc_table(struct drm_i915_private *i915, struct sg_table *st, in shmem_sg_alloc_table() argument
121 i915_gem_shrink(NULL, i915, 2 * page_count, NULL, *s++); in shmem_sg_alloc_table()
207 struct drm_i915_private *i915 = to_i915(obj->base.dev); in shmem_get_pages() local
210 unsigned int max_segment = i915_sg_segment_size(i915->drm.dev); in shmem_get_pages()
227 ret = shmem_sg_alloc_table(i915, st, obj->base.size, mem, mapping, in shmem_get_pages()
246 dev_warn(i915->drm.dev, in shmem_get_pages()
350 struct drm_i915_private *i915 = to_i915(obj->base.dev); in __i915_gem_object_release_shmem() local
371 if (!HAS_LLC(i915) && !IS_DGFX(i915)) in __i915_gem_object_release_shmem()
486 static int __create_shmem(struct drm_i915_private *i915, in __create_shmem() argument
493 drm_gem_private_object_init(&i915->drm, obj, size); in __create_shmem()
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H A Di915_gemfs.c14 void i915_gemfs_init(struct drm_i915_private *i915) in i915_gemfs_init() argument
33 if (GRAPHICS_VER(i915) < 11 && !i915_vtd_active(i915)) in i915_gemfs_init()
55 i915->mm.gemfs = gemfs; in i915_gemfs_init()
56 drm_info(&i915->drm, "Using Transparent Hugepages\n"); in i915_gemfs_init()
60 drm_notice(&i915->drm, in i915_gemfs_init()
62 GRAPHICS_VER(i915) >= 11 ? " on this platform!" : in i915_gemfs_init()
66 void i915_gemfs_fini(struct drm_i915_private *i915) in i915_gemfs_fini() argument
68 kern_unmount(i915->mm.gemfs); in i915_gemfs_fini()
/linux/tools/testing/selftests/drivers/gpu/
H A Di915.sh3 # Runs hardware independent tests for i915 (drivers/gpu/drm/i915)
5 if ! /sbin/modprobe -q -r i915; then
6 echo "drivers/gpu/i915: [SKIP]"
10 if /sbin/modprobe -q i915 mock_selftests=-1; then
11 /sbin/modprobe -q -r i915
12 echo "drivers/gpu/i915: ok"
14 echo "drivers/gpu/i915: [FAIL]"
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_uc.c28 struct drm_i915_private *i915 = uc_to_gt(uc)->i915; in uc_expand_default_options() local
30 if (i915->params.enable_guc != -1) in uc_expand_default_options()
34 if (GRAPHICS_VER(i915) < 12) { in uc_expand_default_options()
35 i915->params.enable_guc = 0; in uc_expand_default_options()
40 if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915)) { in uc_expand_default_options()
41 i915->params.enable_guc = 0; in uc_expand_default_options()
46 if (IS_ALDERLAKE_S(i915) && !IS_RAPTORLAKE_S(i915)) { in uc_expand_default_options()
47 i915->params.enable_guc = ENABLE_GUC_LOAD_HUC; in uc_expand_default_options()
52 i915->params.enable_guc = ENABLE_GUC_LOAD_HUC | ENABLE_GUC_SUBMISSION; in uc_expand_default_options()
63 ret = i915_inject_probe_error(gt->i915, -ENXIO); in __intel_uc_reset_hw()
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