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/linux/drivers/gpu/drm/i915/
H A Di915_drv.h1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
73 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */
187 /* i915 device parameters */
266 * scheduling within i915, which used to be scheduled on the
378 static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) in to_gt() argument
380 return i915->gt[0]; in to_gt()
391 #define INTEL_INFO(i915) ((i915)->__info) argument
392 #define RUNTIME_INFO(i915) (&(i915)->__runtime) argument
393 #define DRIVER_CAPS(i915) (&(i915)->caps) argument
395 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) argument
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H A Dvlv_sideband.h28 void vlv_iosf_sb_init(struct drm_i915_private *i915);
29 void vlv_iosf_sb_fini(struct drm_i915_private *i915);
31 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
32 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
34 static inline void vlv_bunit_get(struct drm_i915_private *i915) in vlv_bunit_get() argument
36 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT)); in vlv_bunit_get()
39 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
40 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
42 static inline void vlv_bunit_put(struct drm_i915_private *i915) in vlv_bunit_put() argument
44 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT)); in vlv_bunit_put()
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H A Dvlv_sideband.c31 static void __vlv_punit_get(struct drm_i915_private *i915) in __vlv_punit_get() argument
45 if (IS_VALLEYVIEW(i915)) { in __vlv_punit_get()
46 cpu_latency_qos_update_request(&i915->vlv_iosf_sb.qos, 0); in __vlv_punit_get()
51 static void __vlv_punit_put(struct drm_i915_private *i915) in __vlv_punit_put() argument
53 if (IS_VALLEYVIEW(i915)) in __vlv_punit_put()
54 cpu_latency_qos_update_request(&i915->vlv_iosf_sb.qos, in __vlv_punit_put()
60 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports) in vlv_iosf_sb_get() argument
63 __vlv_punit_get(i915); in vlv_iosf_sb_get()
65 mutex_lock(&i915->vlv_iosf_sb.lock); in vlv_iosf_sb_get()
68 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports) in vlv_iosf_sb_put() argument
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H A Di915_getparam.c18 struct drm_i915_private *i915 = to_i915(dev); in i915_getparam_ioctl() local
19 struct intel_display *display = &i915->display; in i915_getparam_ioctl()
21 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in i915_getparam_ioctl()
39 value = to_gt(i915)->ggtt->num_fences; in i915_getparam_ioctl()
45 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
49 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
53 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
57 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
61 value = HAS_LLC(i915); in i915_getparam_ioctl()
64 value = HAS_WT(i915); in i915_getparam_ioctl()
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H A Di915_driver.c1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
119 * The i915 workqueue is primarily used for batched retirement of in i915_workqueues_init()
132 dev_priv->wq = alloc_ordered_workqueue("i915", 0); in i915_workqueues_init()
136 dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); in i915_workqueues_init()
141 * The unordered i915 workqueue should be used for all work in i915_workqueues_init()
146 dev_priv->unordered_wq = alloc_workqueue("i915-unordered", 0, 0); in i915_workqueues_init()
202 static void sanitize_gpu(struct drm_i915_private *i915) in sanitize_gpu() argument
204 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) { in sanitize_gpu()
208 for_each_gt(gt, i915, i) in sanitize_gpu()
377 * @i915: valid i915 instance
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H A Di915_switcheroo.c15 struct drm_i915_private *i915 = pdev_to_i915(pdev); in i915_switcheroo_set_state() local
18 if (!i915) { in i915_switcheroo_set_state()
22 if (!HAS_DISPLAY(i915)) { in i915_switcheroo_set_state()
28 drm_info(&i915->drm, "switched on\n"); in i915_switcheroo_set_state()
29 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING; in i915_switcheroo_set_state()
30 /* i915 resume handler doesn't set to D0 */ in i915_switcheroo_set_state()
32 i915_driver_resume_switcheroo(i915); in i915_switcheroo_set_state()
33 i915->drm.switch_power_state = DRM_SWITCH_POWER_ON; in i915_switcheroo_set_state()
35 drm_info(&i915->drm, "switched off\n"); in i915_switcheroo_set_state()
36 i915->drm.switch_power_state = DRM_SWITCH_POWER_CHANGING; in i915_switcheroo_set_state()
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H A Dintel_sbi.c13 static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg, in intel_sbi_rw() argument
17 struct intel_uncore *uncore = &i915->uncore; in intel_sbi_rw()
20 lockdep_assert_held(&i915->sbi_lock); in intel_sbi_rw()
25 drm_err(&i915->drm, in intel_sbi_rw()
44 drm_err(&i915->drm, in intel_sbi_rw()
50 drm_err(&i915->drm, "error during SBI read of reg %x\n", reg); in intel_sbi_rw()
60 void intel_sbi_lock(struct drm_i915_private *i915) in intel_sbi_lock() argument
62 mutex_lock(&i915->sbi_lock); in intel_sbi_lock()
65 void intel_sbi_unlock(struct drm_i915_private *i915) in intel_sbi_unlock() argument
67 mutex_unlock(&i915->sbi_lock); in intel_sbi_unlock()
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H A Dintel_step.c135 static u8 gmd_to_intel_step(struct drm_i915_private *i915, in gmd_to_intel_step() argument
141 drm_dbg(&i915->drm, "Using future steppings\n"); in gmd_to_intel_step()
148 void intel_step_init(struct drm_i915_private *i915) in intel_step_init() argument
152 int revid = INTEL_REVID(i915); in intel_step_init()
155 if (HAS_GMD_ID(i915)) { in intel_step_init()
156 step.graphics_step = gmd_to_intel_step(i915, in intel_step_init()
157 &RUNTIME_INFO(i915)->graphics.ip); in intel_step_init()
158 step.media_step = gmd_to_intel_step(i915, in intel_step_init()
159 &RUNTIME_INFO(i915)->media.ip); in intel_step_init()
161 RUNTIME_INFO(i915)->step = step; in intel_step_init()
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/linux/drivers/gpu/drm/xe/
H A DMakefile151 # i915 Display compat #defines and #includes
154 -I$(src)/compat-i915-headers \
155 -I$(srctree)/drivers/gpu/drm/i915/display/ \
158 # Rule to build SOC code shared with i915
159 $(obj)/i915-soc/%.o: $(srctree)/drivers/gpu/drm/i915/soc/%.c FORCE
163 # Rule to build display code shared with i915
164 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
185 # SOC code shared with i915
187 i915-soc/intel_dram.o \
188 i915-soc/intel_pch.o \
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/linux/drivers/gpu/drm/i915/soc/
H A Dintel_gmch.c22 int intel_gmch_bridge_setup(struct drm_i915_private *i915) in intel_gmch_bridge_setup() argument
24 int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus); in intel_gmch_bridge_setup()
26 i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)); in intel_gmch_bridge_setup()
27 if (!i915->gmch.pdev) { in intel_gmch_bridge_setup()
28 drm_err(&i915->drm, "bridge device not found\n"); in intel_gmch_bridge_setup()
32 return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release, in intel_gmch_bridge_setup()
33 i915->gmch.pdev); in intel_gmch_bridge_setup()
36 static int mchbar_reg(struct drm_i915_private *i915) in mchbar_reg() argument
38 return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915; in mchbar_reg()
43 intel_alloc_mchbar_resource(struct drm_i915_private *i915) in intel_alloc_mchbar_resource() argument
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/linux/drivers/gpu/drm/i915/selftests/
H A Dmock_gem_device.c46 void mock_device_flush(struct drm_i915_private *i915) in mock_device_flush() argument
48 struct intel_gt *gt = to_gt(i915); in mock_device_flush()
61 struct drm_i915_private *i915 = to_i915(dev); in mock_device_release() local
63 if (!i915->do_release) in mock_device_release()
66 mock_device_flush(i915); in mock_device_release()
67 intel_gt_driver_remove(to_gt(i915)); in mock_device_release()
69 i915_gem_drain_workqueue(i915); in mock_device_release()
71 mock_fini_ggtt(to_gt(i915)->ggtt); in mock_device_release()
72 destroy_workqueue(i915->unordered_wq); in mock_device_release()
73 destroy_workqueue(i915->wq); in mock_device_release()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_audio.c66 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
191 static bool needs_wa_14020863754(struct drm_i915_private *i915) in needs_wa_14020863754() argument
193 return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915)); in needs_wa_14020863754()
199 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in audio_config_hdmi_pixel_clock() local
209 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
213 drm_dbg_kms(&i915->drm, in audio_config_hdmi_pixel_clock()
219 drm_dbg_kms(&i915->drm, in audio_config_hdmi_pixel_clock()
254 static int g4x_eld_buffer_size(struct drm_i915_private *i915) in g4x_eld_buffer_size() argument
258 tmp = intel_de_read(i915, G4X_AUD_CNTL_ST); in g4x_eld_buffer_size()
266 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in g4x_audio_codec_get_config() local
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H A Dintel_dkl_phy.c15 * @i915: i915 device instance
17 void intel_dkl_phy_init(struct drm_i915_private *i915) in intel_dkl_phy_init() argument
19 spin_lock_init(&i915->display.dkl.phy_lock); in intel_dkl_phy_init()
23 dkl_phy_set_hip_idx(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) in dkl_phy_set_hip_idx() argument
27 drm_WARN_ON(&i915->drm, tc_port < TC_PORT_1 || tc_port >= I915_MAX_TC_PORTS); in dkl_phy_set_hip_idx()
29 intel_de_write(i915, in dkl_phy_set_hip_idx()
36 * @i915: i915 device instance
44 intel_dkl_phy_read(struct drm_i915_private *i915, struct intel_dkl_phy_reg reg) in intel_dkl_phy_read() argument
48 spin_lock(&i915->display.dkl.phy_lock); in intel_dkl_phy_read()
50 dkl_phy_set_hip_idx(i915, reg); in intel_dkl_phy_read()
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H A Dintel_backlight.c107 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_backlight_set_pwm_level() local
110 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] set backlight PWM = %d\n", in intel_backlight_set_pwm_level()
117 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_backlight_level_to_pwm() local
120 drm_WARN_ON_ONCE(&i915->drm, in intel_backlight_level_to_pwm()
148 struct drm_i915_private *i915 = to_i915(connector->base.dev); in lpt_get_backlight() local
150 return intel_de_read(i915, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
155 struct drm_i915_private *i915 = to_i915(connector->base.dev); in pch_get_backlight() local
157 return intel_de_read(i915, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
162 struct drm_i915_private *i915 = to_i915(connector->base.dev); in i9xx_get_backlight() local
166 val = intel_de_read(i915, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
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H A Dintel_dpll_mgr.c68 void (*enable)(struct drm_i915_private *i915,
77 void (*disable)(struct drm_i915_private *i915,
85 bool (*get_hw_state)(struct drm_i915_private *i915,
93 int (*get_freq)(struct drm_i915_private *i915,
112 void (*update_ref_clks)(struct drm_i915_private *i915);
120 intel_atomic_duplicate_dpll_state(struct drm_i915_private *i915, in intel_atomic_duplicate_dpll_state() argument
127 for_each_shared_dpll(i915, pll, i) in intel_atomic_duplicate_dpll_state()
150 * @i915: i915 device instance
157 intel_get_shared_dpll_by_id(struct drm_i915_private *i915, in intel_get_shared_dpll_by_id() argument
163 for_each_shared_dpll(i915, pll, i) { in intel_get_shared_dpll_by_id()
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H A Dintel_modeset_setup.c39 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_crtc_disable_noatomic_begin() local
50 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in intel_crtc_disable_noatomic_begin()
58 state = drm_atomic_state_alloc(&i915->drm); in intel_crtc_disable_noatomic_begin()
60 drm_dbg_kms(&i915->drm, in intel_crtc_disable_noatomic_begin()
70 for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, in intel_crtc_disable_noatomic_begin()
79 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret); in intel_crtc_disable_noatomic_begin()
82 i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc); in intel_crtc_disable_noatomic_begin()
86 drm_dbg_kms(&i915->drm, in intel_crtc_disable_noatomic_begin()
120 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in reset_encoder_connector_state() local
122 to_intel_pmdemand_state(i915->display.pmdemand.obj.state); in reset_encoder_connector_state()
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H A Dintel_hotplug_irq.c392 static u32 intel_hpd_hotplug_mask(struct drm_i915_private *i915, in intel_hpd_hotplug_mask() argument
404 static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915, in intel_hpd_hotplug_enables() argument
410 for_each_intel_encoder(&i915->drm, encoder) in intel_hpd_hotplug_enables()
515 void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir) in xelpdp_pica_irq_handler() argument
517 struct intel_display *display = &i915->display; in xelpdp_pica_irq_handler()
523 if (DISPLAY_VER(i915) >= 20) in xelpdp_pica_irq_handler()
529 if (!(i915->display.hotplug.hpd[pin] & hotplug_trigger)) in xelpdp_pica_irq_handler()
534 val = intel_de_read(i915, XELPDP_PORT_HOTPLUG_CTL(pin)); in xelpdp_pica_irq_handler()
535 intel_de_write(i915, XELPDP_PORT_HOTPLUG_CTL(pin), val); in xelpdp_pica_irq_handler()
542 drm_dbg(&i915->drm, in xelpdp_pica_irq_handler()
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H A Dintel_tc.c180 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_tc_cold_requires_aux_pw() local
184 intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch); in intel_tc_cold_requires_aux_pw()
190 struct drm_i915_private *i915 = tc_to_i915(tc); in __tc_cold_block() local
194 return intel_display_power_get(i915, *domain); in __tc_cold_block()
214 struct drm_i915_private *i915 = tc_to_i915(tc); in __tc_cold_unblock() local
216 intel_display_power_put(i915, domain, wakeref); in __tc_cold_unblock()
233 struct drm_i915_private *i915 = tc_to_i915(tc); in assert_display_core_power_enabled() local
235 drm_WARN_ON(&i915->drm, in assert_display_core_power_enabled()
236 !intel_display_power_is_enabled(i915, POWER_DOMAIN_DISPLAY_CORE)); in assert_display_core_power_enabled()
242 struct drm_i915_private *i915 = tc_to_i915(tc); in assert_tc_cold_blocked() local
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H A Dskl_watermark.c37 static void skl_sagv_disable(struct drm_i915_private *i915);
55 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915) in intel_enabled_dbuf_slices_mask() argument
60 for_each_dbuf_slice(i915, slice) { in intel_enabled_dbuf_slices_mask()
61 if (intel_de_read(i915, DBUF_CTL_S(slice)) & DBUF_POWER_STATE) in intel_enabled_dbuf_slices_mask()
72 static bool skl_needs_memory_bw_wa(struct drm_i915_private *i915) in skl_needs_memory_bw_wa() argument
74 return DISPLAY_VER(i915) == 9; in skl_needs_memory_bw_wa()
78 intel_has_sagv(struct drm_i915_private *i915) in intel_has_sagv() argument
80 struct intel_display *display = &i915->display; in intel_has_sagv()
86 intel_sagv_block_time(struct drm_i915_private *i915) in intel_sagv_block_time() argument
88 struct intel_display *display = &i915->display; in intel_sagv_block_time()
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H A Dintel_display_power.h194 void __intel_display_power_put_async(struct drm_i915_private *i915,
198 void intel_display_power_flush_work(struct drm_i915_private *i915);
204 intel_display_power_put_async(struct drm_i915_private *i915, in intel_display_power_put_async() argument
208 __intel_display_power_put_async(i915, domain, wakeref, -1); in intel_display_power_put_async()
212 intel_display_power_put_async_delay(struct drm_i915_private *i915, in intel_display_power_put_async_delay() argument
217 __intel_display_power_put_async(i915, domain, wakeref, delay_ms); in intel_display_power_put_async_delay()
224 intel_display_power_put(struct drm_i915_private *i915, in intel_display_power_put() argument
228 intel_display_power_put_unchecked(i915, domain); in intel_display_power_put()
232 intel_display_power_put_async(struct drm_i915_private *i915, in intel_display_power_put_async() argument
236 __intel_display_power_put_async(i915, domain, INTEL_WAKEREF_DEF, -1); in intel_display_power_put_async()
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/linux/drivers/gpu/drm/xe/compat-i915-headers/
H A Dvlv_sideband.h27 static inline void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports) in vlv_iosf_sb_get() argument
30 static inline u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg) in vlv_iosf_sb_read() argument
34 static inline void vlv_iosf_sb_write(struct drm_i915_private *i915, in vlv_iosf_sb_write() argument
38 static inline void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports) in vlv_iosf_sb_put() argument
41 static inline void vlv_bunit_get(struct drm_i915_private *i915) in vlv_bunit_get() argument
44 static inline u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg) in vlv_bunit_read() argument
48 static inline void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val) in vlv_bunit_write() argument
51 static inline void vlv_bunit_put(struct drm_i915_private *i915) in vlv_bunit_put() argument
54 static inline void vlv_cck_get(struct drm_i915_private *i915) in vlv_cck_get() argument
57 static inline u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg) in vlv_cck_read() argument
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/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_tee.c63 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_tee_io_message() local
70 * The binding of the component is asynchronous from i915 probe, so we in intel_pxp_tee_io_message()
81 drm_err(&i915->drm, "Failed to send PXP TEE message\n"); in intel_pxp_tee_io_message()
88 drm_err(&i915->drm, "Failed to receive PXP TEE message\n"); in intel_pxp_tee_io_message()
93 drm_err(&i915->drm, in intel_pxp_tee_io_message()
115 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_tee_stream_message() local
140 drm_err(&i915->drm, "Failed to send PXP TEE gsc command\n"); in intel_pxp_tee_stream_message()
151 * @i915_kdev: pointer to i915 kernel device
162 struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); in i915_pxp_tee_component_bind() local
163 struct intel_pxp *pxp = i915->pxp; in i915_pxp_tee_component_bind()
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rps.c43 return rps_to_gt(rps)->i915; in rps_to_i915()
139 queue_work(gt->i915->unordered_wq, &rps->work); in rps_timer()
144 queue_work(gt->i915->unordered_wq, &rps->work); in rps_timer()
227 if (GRAPHICS_VER(gt->i915) >= 11) in rps_reset_interrupts()
247 intel_synchronize_irq(gt->i915); in rps_disable_interrupts()
277 struct drm_i915_private *i915 = rps_to_i915(rps); in gen5_rps_init() local
283 if (i915->fsb_freq <= 3200000) in gen5_rps_init()
285 else if (i915->fsb_freq <= 4800000) in gen5_rps_init()
292 cparams[i].t == DIV_ROUND_CLOSEST(i915->mem_freq, 1000)) { in gen5_rps_init()
306 drm_dbg(&i915->drm, "fmax: %d, fmin: %d, fstart: %d\n", in gen5_rps_init()
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H A Dintel_region_lmem.c32 _resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size) in _resize_bar() argument
34 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in _resize_bar()
42 drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n", in _resize_bar()
47 drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size); in _resize_bar()
50 static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size) in i915_resize_lmem_bar() argument
52 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in i915_resize_lmem_bar()
63 if (i915->params.lmem_bar_size) { in i915_resize_lmem_bar()
66 rebar_size = i915->params.lmem_bar_size * in i915_resize_lmem_bar()
77 drm_info(&i915->drm, in i915_resize_lmem_bar()
102 drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n"); in i915_resize_lmem_bar()
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/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_mman.c97 struct drm_i915_private *i915 = to_i915(obj->base.dev); in check_partial_mapping() local
155 intel_gt_flush_ggtt_writes(to_gt(i915)); in check_partial_mapping()
191 struct drm_i915_private *i915 = to_i915(obj->base.dev); in check_partial_mappings() local
251 intel_gt_flush_ggtt_writes(to_gt(i915)); in check_partial_mappings()
290 setup_tile_size(struct tile *tile, struct drm_i915_private *i915) in setup_tile_size() argument
292 if (GRAPHICS_VER(i915) <= 2) { in setup_tile_size()
297 HAS_128_BYTE_Y_TILING(i915)) { in setup_tile_size()
307 if (GRAPHICS_VER(i915) < 4) in setup_tile_size()
309 else if (GRAPHICS_VER(i915) < 7) in setup_tile_size()
318 struct drm_i915_private *i915 = arg; in igt_partial_tiling() local
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