| /linux/Documentation/i2c/ |
| H A D | i2c-sysfs.rst | 4 Linux I2C Sysfs
10 I2C topology can be complex because of the existence of I2C MUX
11 (I2C Multiplexer). The Linux
12 kernel abstracts the MUX channels into logical I2C bus numbers. However, there
13 is a gap of knowledge to map from the I2C bus physical number and MUX topology
14 to logical I2C bus number. This doc is aimed to fill in this gap, so the
16 the concept of logical I2C buses in the kernel, by knowing the physical I2C
17 topology and navigating through the I2C sysfs in Linux shell. This knowledge is
18 useful and essential to use ``i2c-tools`` for the purpose of development and
24 People who need to use Linux shell to interact with I2C subsystem on a system
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| /linux/drivers/i2c/busses/ |
| H A D | Makefile | 3 # Makefile for the i2c bus drivers.
7 obj-$(CONFIG_I2C_SCMI) += i2c-scmi.o
9 # Auxiliary I2C/SMBus modules
10 obj-$(CONFIG_I2C_CCGX_UCSI) += i2c-ccgx-ucsi.o
13 obj-$(CONFIG_I2C_ALI1535) += i2c-ali1535.o
14 obj-$(CONFIG_I2C_ALI1563) += i2c-ali1563.o
15 obj-$(CONFIG_I2C_ALI15X3) += i2c-ali15x3.o
16 obj-$(CONFIG_I2C_AMD756) += i2c-amd756.o
17 obj-$(CONFIG_I2C_AMD8111) += i2c-amd8111.o
18 obj-$(CONFIG_I2C_CHT_WC) += i2c-cht-wc.o
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| H A D | i2c-pxa.c | 5 * I2C adapter for the PXA I2C bus access.
24 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-pxa.h>
38 /* I2C register field definitions */
112 * 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
113 * 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
115 * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
124 /* I2C status register init values
155 /* I2C register layout definitions */
207 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
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| H A D | i2c-xiic.c | 3 * i2c-xiic.c
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
36 #define DRIVER_NAME "xiic-i2c"
58 * struct xiic_i2c - Internal representation of the XIIC I2C bus
77 * @input_clk: Input clock to I2C controller
78 * @i2c_clk: I2C SCL frequency
114 * struct timing_regs - AXI I2C timing registers that depend on I2C spec
129 /* Reg values in ns derived from I2C spec and AXI I2C PG for different frequencies */
156 * setting i2c clock frequency for the line.
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| H A D | i2c-digicolor.c | 3 * I2C bus driver for Conexant Digicolor SoCs
13 #include <linux/i2c.h>
71 static void dc_i2c_cmd(struct dc_i2c *i2c, u8 cmd) in dc_i2c_cmd() argument
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
86 static void dc_i2c_data(struct dc_i2c *i2c, u8 data) in dc_i2c_data() argument
88 writeb_relaxed(data, i2c->regs + II_DATA); in dc_i2c_data()
91 static void dc_i2c_write_byte(struct dc_i2c *i2c, u8 byte) in dc_i2c_write_byte() argument
93 dc_i2c_data(i2c, byte); in dc_i2c_write_byte()
94 dc_i2c_cmd(i2c, II_CMD_SEND_ACK); in dc_i2c_write_byte()
97 static void dc_i2c_write_buf(struct dc_i2c *i2c) in dc_i2c_write_buf() argument
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| H A D | i2c-jz4780.c | 3 * Ingenic JZ4780 I2C bus driver
15 #include <linux/i2c.h>
171 static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c, in jz4780_i2c_readw() argument
174 return readw(i2c->iomem + offset); in jz4780_i2c_readw()
177 static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c, in jz4780_i2c_writew() argument
180 writew(val, i2c->iomem + offset); in jz4780_i2c_writew()
183 static int jz4780_i2c_disable(struct jz4780_i2c *i2c) in jz4780_i2c_disable() argument
188 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0); in jz4780_i2c_disable()
191 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); in jz4780_i2c_disable()
198 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval); in jz4780_i2c_disable()
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| H A D | i2c-k1.c | 7 #include <linux/i2c.h>
13 /* spacemit i2c registers */
56 #define SPACEMIT_SR_IBB BIT(16) /* i2c bus busy */
83 /* i2c bus recover timeout: us */
98 /* i2c-spacemit driver's main struct */
123 static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c) in spacemit_i2c_enable() argument
127 val = readl(i2c->base + SPACEMIT_ICR); in spacemit_i2c_enable()
129 writel(val, i2c->base + SPACEMIT_ICR); in spacemit_i2c_enable()
132 static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c) in spacemit_i2c_disable() argument
136 val = readl(i2c->base + SPACEMIT_ICR); in spacemit_i2c_disable()
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| H A D | i2c-s3c2410.c | 2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
7 * S3C2410 I2C Controller
13 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
87 /* i2c controller state */
125 .name = "s3c2410-i2c",
128 .name = "s3c2440-i2c",
131 .name = "s3c2440-hdmiphy-i2c",
137 static void i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
141 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
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| H A D | i2c-img-scb.c | 3 * I2C adapter for the IMG Serial Control Bus (SCB) IP block.
7 * There are three ways that this I2C controller can be driven:
15 * - Atomic commands. A low level I2C symbol (such as generate
20 * This mode of operation is used by MODE_ATOMIC, which uses an I2C
21 * state machine in the interrupt handler to compose/react to I2C
26 * in suboptimal use of the bus, with gaps between the I2C symbols while
30 * specified, and the hardware takes care of the I2C state machine,
31 * using a FIFO to send/receive bytes of data to an I2C slave. The
36 * with control of repeated start bits between I2C messages.
40 * no wasted time between I2C symbols or I2C messages.
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| H A D | i2c-synquacer.c | 12 #include <linux/i2c.h>
25 /* I2C register address definitions */
35 /* I2C register bit definitions */
113 /* min I2C clock frequency 14M */
115 /* max I2C clock frequency 200M */
117 /* I2C clock frequency 18M */
148 static inline int is_lastmsg(struct synquacer_i2c *i2c) in is_lastmsg() argument
150 return i2c->msg_idx >= (i2c->msg_num - 1); in is_lastmsg()
153 static inline int is_msglast(struct synquacer_i2c *i2c) in is_msglast() argument
155 return i2c->msg_ptr == (i2c->msg->len - 1); in is_msglast()
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| H A D | Kconfig | 6 menu "I2C Hardware Bus support"
29 will be called i2c-ali1535.
41 will be called i2c-ali1563.
48 Acer Labs Inc. (ALI) M1514 and M1543 motherboard I2C interfaces.
51 will be called i2c-ali15x3.
58 756/766/768 mainboard I2C interfaces. The driver also includes
59 support for the first (SMBus 1.0) I2C interface of the AMD 8111 and
60 the nVidia nForce I2C interface.
63 will be called i2c-amd756.
70 second (SMBus 2.0) AMD 8111 mainboard I2C interface.
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| H A D | i2c-meson.c | 3 * I2C bus driver for Amlogic Meson SoCs
11 #include <linux/i2c.h>
21 /* Meson I2C register map */
68 * struct meson_i2c - Meson I2C device private data
70 * @adap: I2C adapter instance
74 * @msg: Pointer to the current I2C message
108 void (*set_clk_div)(struct meson_i2c *i2c, unsigned int freq);
111 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask, in meson_i2c_set_mask() argument
116 data = readl(i2c->regs + reg); in meson_i2c_set_mask()
119 writel(data, i2c->regs + reg); in meson_i2c_set_mask()
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| H A D | i2c-lpc2k.c | 5 * Code portions referenced from the i2x-pxa and i2c-pnx drivers
17 #include <linux/i2c.h>
46 /* I2C SCL clock has different duty cycle depending on mode */
52 * 26 possible I2C status codes, but codes applicable only
83 static void i2c_lpc2k_reset(struct lpc2k_i2c *i2c) in i2c_lpc2k_reset() argument
86 writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_reset()
87 writel(0, i2c->base + LPC24XX_I2ADDR); in i2c_lpc2k_reset()
88 writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET); in i2c_lpc2k_reset()
91 static int i2c_lpc2k_clear_arb(struct lpc2k_i2c *i2c) in i2c_lpc2k_clear_arb() argument
99 writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET); in i2c_lpc2k_clear_arb()
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| H A D | i2c-mt65xx.c | 14 #include <linux/i2c.h>
85 #define I2C_DRV_NAME "i2c-mt65xx"
88 * enum i2c_mt65xx_clks - Clocks enumeration for MT65XX I2C
90 * @I2C_MT65XX_CLK_MAIN: main clock for i2c bus
91 * @I2C_MT65XX_CLK_DMA: DMA clock for i2c via DMA
92 * @I2C_MT65XX_CLK_PMIC: PMIC clock for i2c from PMIC
93 * @I2C_MT65XX_CLK_ARB: Arbitrator clock for i2c
287 struct i2c_adapter adap; /* i2c host adapter */
292 /* set in i2c probe */
293 void __iomem *base; /* i2c base addr */
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| H A D | i2c-octeon-core.c | 7 * This file contains the shared part of the driver for the i2c adapter in
16 #include <linux/i2c.h>
22 #include "i2c-octeon-core.h"
31 struct octeon_i2c *i2c = dev_id; in octeon_i2c_isr() local
33 i2c->int_disable(i2c); in octeon_i2c_isr()
34 wake_up(&i2c->queue); in octeon_i2c_isr()
39 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c) in octeon_i2c_test_iflg() argument
41 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG); in octeon_i2c_test_iflg()
46 * @i2c: The struct octeon_i2c
50 static int octeon_i2c_wait(struct octeon_i2c *i2c) in octeon_i2c_wait() argument
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| H A D | i2c-exynos5.c | 3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
11 #include <linux/i2c.h>
206 /* Version of HS-I2C Hardware */
213 * @hw: the hardware variant of Exynos I2C controller
272 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) in exynos5_i2c_clr_pend_irq() argument
274 writel(readl(i2c->regs + HSI2C_INT_STATUS), in exynos5_i2c_clr_pend_irq()
275 i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_clr_pend_irq()
288 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) in exynos5_i2c_set_timing() argument
300 unsigned int clkin = clk_get_rate(i2c->clk); in exynos5_i2c_set_timing()
301 unsigned int op_clk = hs_timings ? i2c->op_clock : in exynos5_i2c_set_timing()
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| H A D | i2c-thunderx-pcidrv.c | 2 * Cavium ThunderX i2c driver.
16 #include <linux/i2c.h>
17 #include <linux/i2c-smbus.h>
24 #include "i2c-octeon-core.h"
26 #define DRV_NAME "i2c-thunderx"
41 static void thunder_i2c_int_enable(struct octeon_i2c *i2c) in thunder_i2c_int_enable() argument
44 i2c->twsi_base + TWSI_INT_ENA_W1S); in thunder_i2c_int_enable()
50 static void thunder_i2c_int_disable(struct octeon_i2c *i2c) in thunder_i2c_int_disable() argument
53 i2c->twsi_base + TWSI_INT_ENA_W1C); in thunder_i2c_int_disable()
56 static void thunder_i2c_hlc_int_enable(struct octeon_i2c *i2c) in thunder_i2c_hlc_int_enable() argument
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| H A D | i2c-mpc.c | 3 * This is a combined i2c adapter and algorithm driver for the
5 * the same I2C unit (8240, 8245, 85xx).
25 #include <linux/i2c.h>
109 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
112 static inline void writeccr(struct mpc_i2c *i2c, u32 x) in writeccr() argument
114 writeb(x, i2c->base + MPC_I2C_CR); in writeccr()
122 static void mpc_i2c_fixup(struct mpc_i2c *i2c) in mpc_i2c_fixup() argument
128 writeccr(i2c, 0); in mpc_i2c_fixup()
129 writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */ in mpc_i2c_fixup()
130 writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */ in mpc_i2c_fixup()
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| H A D | i2c-viai2c-common.c | 3 #include "i2c-viai2c-common.h"
5 int viai2c_wait_bus_not_busy(struct viai2c *i2c) in viai2c_wait_bus_not_busy() argument
10 while (!(readw(i2c->base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) { in viai2c_wait_bus_not_busy()
12 dev_warn(i2c->dev, "timeout waiting for bus ready\n"); in viai2c_wait_bus_not_busy()
22 static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) in viai2c_write() argument
24 u16 val, tcr_val = i2c->tcr; in viai2c_write()
26 i2c->last = last; in viai2c_write()
33 i2c->xfered_len = -1; in viai2c_write()
34 writew(0, i2c->base + VIAI2C_REG_CDR); in viai2c_write()
36 writew(pmsg->buf[0] & 0xFF, i2c->base + VIAI2C_REG_CDR); in viai2c_write()
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| H A D | i2c-mchp-pci1xxxx.c | 3 * Microchip PCI1XXXX I2C adapter driver for PCIe Switch
4 * which has I2C controller in one of its downstream functions
14 #include <linux/i2c.h>
15 #include <linux/i2c-smbus.h>
103 * BUS_CLK_XK_LOW_PERIOD_TICKS field defines the number of I2C Baud Clock
104 * periods that make up the low phase of the I2C/SMBus bus clock at X KHz.
111 * BUS_CLK_XK_HIGH_PERIOD_TICKS field defines the number of I2C Baud Clock
112 * periods that make up the high phase of the I2C/SMBus bus clock at X KHz.
334 static int set_sys_lock(struct pci1xxxx_i2c *i2c) in set_sys_lock() argument
336 void __iomem *p = i2c->i2c_base + SMB_GPR_LOCK_REG; in set_sys_lock()
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| H A D | i2c-mxs.c | 3 * Freescale MXS I2C bus driver
16 #include <linux/i2c.h>
29 #define DRIVER_NAME "mxs-i2c"
69 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0) argument
71 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8) argument
103 * struct mxs_i2c_dev - per device, private MXS-I2C data
110 * @adapter: i2c subsystem adapter node
132 static int mxs_i2c_reset(struct mxs_i2c_dev *i2c) in mxs_i2c_reset() argument
134 int ret = stmp_reset_block(i2c->regs); in mxs_i2c_reset()
139 * Configure timing for the I2C block. The I2C TIMING2 register has to in mxs_i2c_reset()
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| /linux/drivers/media/pci/netup_unidvb/ |
| H A D | netup_unidvb_i2c.c | 5 * Internal I2C bus driver for NetUP Universal Dual DVB-CI
65 irqreturn_t netup_i2c_interrupt(struct netup_i2c *i2c) in netup_i2c_interrupt() argument
71 spin_lock_irqsave(&i2c->lock, flags); in netup_i2c_interrupt()
72 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
73 writew(reg & ~TWI_IRQEN, &i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
74 dev_dbg(i2c->adap.dev.parent, in netup_i2c_interrupt()
77 dev_dbg(i2c->adap.dev.parent, in netup_i2c_interrupt()
79 i2c->state = STATE_DONE; in netup_i2c_interrupt()
83 dev_dbg(i2c->adap.dev.parent, in netup_i2c_interrupt()
85 i2c->state = STATE_ERROR; in netup_i2c_interrupt()
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| /linux/drivers/i2c/ |
| H A D | Kconfig | 3 # I2C subsystem configuration
6 menu "I2C support"
8 config I2C config
9 tristate "I2C support"
13 I2C (pronounce: I-squared-C) is a slow serial bus protocol used in
15 or System Management Bus is a subset of the I2C protocol. More
16 information is contained in the directory <file:Documentation/i2c/>,
19 Both I2C and SMBus are supported here. You will need this for
22 If you want I2C support, you should say Y here and also to the
25 This I2C support can also be built as a module. If so, the module
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| /linux/Documentation/devicetree/bindings/i2c/ |
| H A D | nvidia,tegra20-i2c.yaml | 4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
11 title: NVIDIA Tegra I2C controller driver
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
21 - description: Tegra20 has specific I2C controller called as DVC I2C
22 controller. This only support master mode of I2C communication.
24 generic I2C controller. Driver of DVC I2C controller is only
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| /linux/arch/arm/boot/dts/aspeed/ |
| H A D | aspeed-bmc-facebook-cmm.dts | 319 * I2C bus reserved for communication with COM-E.
326 * I2C bus to Line Cards and Fabric Cards.
331 i2c-mux@77 {
336 i2c-mux-idle-disconnect;
339 imux16: i2c@0 {
344 i2c-mux@70 {
349 i2c-mux-idle-disconnect;
351 imux104: i2c@0 {
356 imux105: i2c@1 {
361 imux106: i2c@2 {
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