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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mpc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C-Bus adapter for MPC824x/83xx/85xx/86xx/512x/52xx SoCs
10 - Chris Packham <chris.packham@alliedtelesis.co.nz>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - items:
19 - enum:
20 - mpc5200-i2c
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/linux/drivers/i2c/busses/
H A Di2c-designware-master.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
16 #include <linux/i2c.h>
27 #include "i2c-designware-core.h"
36 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
37 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
39 /* Configure the I2C master */ in i2c_dw_configure_fifo_master()
40 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
47 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
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H A Di2c-mpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * This is a combined i2c adapter and algorithm driver for the
5 * the same I2C unit (8240, 8245, 85xx).
7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
25 #include <linux/i2c.h>
109 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
112 static inline void writeccr(struct mpc_i2c *i2c, u32 x) in writeccr() argument
114 writeb(x, i2c->base + MPC_I2C_CR); in writeccr()
122 static void mpc_i2c_fixup(struct mpc_i2c *i2c) in mpc_i2c_fixup() argument
127 for (k = 9; k; k--) { in mpc_i2c_fixup()
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H A Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
7 * S3C2410 I2C Controller
13 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
81 /* Max time to wait for bus to become idle after a xfer (in us) */
87 /* i2c controller state */
125 .name = "s3c2410-i2c",
128 .name = "s3c2440-i2c",
131 .name = "s3c2440-hdmiphy-i2c",
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H A Di2c-hisi.c1 // SPDX-License-Identifier: GPL-2.0
3 * HiSilicon I2C Controller Driver for Kunpeng SoC
12 #include <linux/i2c.h>
97 /* Intermediates for recording the transfer process */
108 /* I2C bus configuration */
116 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_enable_int()
121 writel_relaxed((~mask) & HISI_I2C_INT_ALL, ctlr->iobase + HISI_I2C_INT_MASK); in hisi_i2c_disable_int()
126 writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); in hisi_i2c_clear_int()
131 writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); in hisi_i2c_clear_tx_int()
136 u32 int_err = ctlr->xfer_err, reg; in hisi_i2c_handle_errors()
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H A Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
18 #include <linux/i2c.h>
34 #include "i2c-designware-core.h"
64 "incorrect slave-transmitter mode configuration",
71 *val = readl(dev->base + reg); in dw_reg_read()
80 writel(val, dev->base + reg); in dw_reg_write()
89 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
98 writel(swab32(val), dev->base + reg); in dw_reg_write_swab()
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H A Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
6 * I2C master mode controller driver, used in Nomadik 8815
11 * - The memory bus only supports 32-bit accesses.
12 * - (only EyeQ5) A register must be configured for the I2C speed mode;
22 #include <linux/i2c.h>
35 #define DRIVER_NAME "nmk-i2c"
37 /* I2C Controller register offsets */
74 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
75 #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */
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H A Di2c-emev2.c1 // SPDX-License-Identifier: GPL-2.0
3 * I2C driver for the Renesas EMEV2 SoC
5 * Copyright (C) 2015 Wolfram Sang <wsa@sang-engineering.com>
7 * Copyright 2010-2015 Renesas Electronics Corporation
13 #include <linux/i2c.h>
23 /* I2C Registers */
34 /* I2C IICACT0 Masks */
37 /* I2C IICC0 Masks */
46 /* I2C IICCL0 Masks */
50 /* I2C IICSE0 Masks */
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H A Di2c-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * I2C adapter for the PXA I2C bus access.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
24 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-pxa.h>
38 /* I2C register field definitions */
45 #define ICR_TB (1 << 3) /* transfer byte bit */
59 #define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
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H A Di2c-imx.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2002 Motorola GSG-China
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
12 * Derived from Motorola GSG China I2C example driver
28 #include <linux/dma-mapping.h>
34 #include <linux/i2c.h>
46 #include <linux/platform_data/i2c-imx.h>
53 #define DRIVER_NAME "imx-i2c"
58 * Enable DMA if transfer byte size is bigger than this threshold.
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H A Di2c-tegra.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
14 #include <linux/dma-mapping.h>
16 #include <linux/i2c.h>
51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
137 /* configuration load timeout in microseconds */
144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
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H A Di2c-rcar.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Renesas R-Car I2C unit
5 * Copyright (C) 2014-19 Wolfram Sang <wsa@sang-engineering.com>
6 * Copyright (C) 2011-2019 Renesas Electronics Corporation
8 * Copyright (C) 2012-14 Renesas Solutions Corp.
11 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
12 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
18 #include <linux/dma-mapping.h>
23 #include <linux/i2c.h>
24 #include <linux/i2c-smbus.h>
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H A Di2c-qup.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
16 #include <linux/i2c.h>
70 /* I2C mini core related values */
125 /* Maximum transfer length for single DMA descriptor */
128 /* Maximum transfer length for all DMA descriptors */
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
145 * data transfer
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H A Di2c-i801.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
15 * I/O Block I2C
18 * ---------------------------------------------------------------------------
43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_i2c.c1 // SPDX-License-Identifier: GPL-2.0-only
19 struct hdmi *hdmi = hdmi_i2c->hdmi; in init_ddc()
33 /* enable reference timer for 27us */ in init_ddc()
41 struct hdmi *hdmi = hdmi_i2c->hdmi; in ddc_clear_irq()
42 struct drm_device *dev = hdmi->dev; in ddc_clear_irq()
47 --retry; in ddc_clear_irq()
58 DRM_DEV_ERROR(dev->dev, "timeout waiting for DDC\n"); in ddc_clear_irq()
59 return -ETIMEDOUT; in ddc_clear_irq()
62 hdmi_i2c->sw_done = false; in ddc_clear_irq()
71 struct hdmi *hdmi = hdmi_i2c->hdmi; in sw_done()
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/linux/drivers/platform/chrome/
H A Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
24 * about 400-500us for the EC to respond there is not a lot of
28 * SPI transfer size is 256 bytes, so at 5MHz we need a response
29 * time of perhaps <320us (200 bytes / 1600 bits).
34 * Allow for a long time for the EC to respond. We support i2c
37 * on the other end and need to transfer ~256 bytes, then we need:
38 * 10 us/bit * ~10 bits/byte * ~256 bytes = ~25ms
43 * not directly passing i2c through, but it's too late for that for
50 * for this, clocking in at 2-3ms.
58 * need at least 70 us with the 16 MHz STM32 EC, so go with 200 us to be
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/linux/drivers/comedi/drivers/
H A Ds626.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
68 * struct s626_private - Working data for s626 driver.
69 * @ai_cmd_running: non-zero if ai_cmd is running.
80 * @i2c_adrs: I2C device address for onboard EEPROM (board rev dependent)
98 #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
110 writel(val, dev->mmio + reg); in s626_mc_enable()
116 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable()
124 val = readl(dev->mmio + reg); in s626_mc_test()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsmu_v11_0_i2c.c34 #include <linux/i2c.h>
50 struct amdgpu_device *adev = smu_i2c->adev; in smu_v11_0_i2c_set_clock_gating()
60 * signalling period for the highest I2C transfer speed used in the
62 * I2C data transfer mode is 400 kb/s, then t_i2c_poll is 25 us." --
79 struct amdgpu_device *adev = smu_i2c->adev; in smu_v11_0_i2c_enable()
86 for (ii = I2C_MAX_T_POLL_COUNT; ii > 0; ii--) { in smu_v11_0_i2c_enable()
105 struct amdgpu_device *adev = smu_i2c->adev; in smu_v11_0_i2c_clear_status()
116 struct amdgpu_device *adev = smu_i2c->adev; in smu_v11_0_i2c_configure()
124 * 1: standard mode, 0 - 100 Kb/s, in smu_v11_0_i2c_configure()
138 struct amdgpu_device *adev = smu_i2c->adev; in smu_v11_0_i2c_set_clock()
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/linux/drivers/media/platform/marvell/
H A Dcafe-driver.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * Copyright 2006-11 One Laptop Per Child Association, Inc.
11 * Copyright 2006-11 Jonathan Corbet <corbet@lwn.net>
23 #include <linux/i2c.h>
28 #include <media/v4l2-device.h>
29 #include <media/i2c/ov7670.h>
36 #include "mcam-core.h"
53 wait_queue_head_t smbus_wait; /* Waiting on i2c events */
57 * Most of the camera controller registers are defined in mcam-core.h,
82 #define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
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/linux/drivers/i3c/master/
H A Dsvc-i3c-master.c1 // SPDX-License-Identifier: GPL-2.0
3 * Silvaco dual-role I3C master driver
162 * struct svc_i3c_master - Silvaco I3C Master structure
170 * @hj_work: Hot-join work
176 * @xferqueue: Transfer queue structure
178 * @xferqueue.cur: Current ongoing transfer
185 * @lock: Transfer lock, protect between IBI work thread and callbacks from master
222 * struct svc_i3c_i2c_dev_data - Device specific data
235 return !!(master->enabled_events & mask); in is_events_enabled()
242 mstatus = readl(master->regs + SVC_I3C_MSTATUS); in svc_i3c_master_error()
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/linux/drivers/media/pci/ivtv/
H A Divtv-i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 I2C functions
4 Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
5 Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
10 This file includes an i2c implementation that was reverse engineered
11 from the Hauppauge windows driver. Older ivtv versions used i2c-algo-bit,
13 CPU on the PVR-150 which handles IR functions (occasional inability to
14 communicate with the chip until it was reset) and also with the i2c
17 The implementation is very similar to i2c-algo-bit, but there are enough
19 employed by i2c-algo-bit is to use udelay() to implement the timing
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/linux/drivers/media/usb/go7007/
H A Dgo7007-driver.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2005-2006 Micronas USA Inc.
15 #include <linux/i2c.h>
22 #include <media/v4l2-common.h>
23 #include <media/v4l2-event.h>
25 #include "go7007-priv.h"
35 go->interrupt_available = 0; in go7007_read_interrupt()
36 go->hpi_ops->read_interrupt(go); in go7007_read_interrupt()
37 if (wait_event_timeout(go->interrupt_waitq, in go7007_read_interrupt()
38 go->interrupt_available, 5*HZ) < 0) { in go7007_read_interrupt()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp_aux.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020-2021 Intel Corporation
25 snprintf(buf, size, "%c", 'A' + aux_ch - AUX_CH_D_XELPD + AUX_CH_D); in aux_ch_name()
27 snprintf(buf, size, "USBC%c", '1' + aux_ch - AUX_CH_USBC1); in aux_ch_name()
42 v |= ((u32)src[i]) << ((3 - i) * 8); in intel_dp_aux_pack()
53 dst[i] = src >> ((3 - i) * 8); in intel_dp_aux_unpack()
60 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); in intel_dp_aux_wait_done()
69 if (ret == -ETIMEDOUT) in intel_dp_aux_wait_done()
70 drm_err(display->drm, in intel_dp_aux_wait_done()
71 "%s: did not complete or timeout within %ums (status 0x%08x)\n", in intel_dp_aux_wait_done()
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/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
172 * This value is in terms of 32-bit words.
191 * @i2c_selection: I2C Selection
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/linux/drivers/macintosh/
H A Dsmu.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * - maybe add timeout to commands ?
12 * - blocking version of time functions
13 * - polling version of i2c commands (including timer that works with
15 * - maybe avoid some data copies with i2c by directly using the smu cmd
17 * - understand SMU -> CPU events and implement reception of them via
91 struct smu_i2c_cmd *cmd_i2c_cur; /* pending i2c command */
116 if (list_empty(&smu->cmd_list)) in smu_start_cmd()
120 cmd = list_entry(smu->cmd_list.next, struct smu_cmd, link); in smu_start_cmd()
121 smu->cmd_cur = cmd; in smu_start_cmd()
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