Lines Matching +full:i2c +full:- +full:transfer +full:- +full:timeout +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2002 Motorola GSG-China
9 * Implementation of I2C Adapter/Algorithm Driver
10 * for I2C Bus integrated in Freescale i.MX/MXC processors
12 * Derived from Motorola GSG China I2C example driver
28 #include <linux/dma-mapping.h>
34 #include <linux/i2c.h>
46 #include <linux/platform_data/i2c-imx.h>
53 #define DRIVER_NAME "imx-i2c"
58 * Enable DMA if transfer byte size is bigger than this threshold.
66 /* IMX I2C registers:
67 * the I2C register offset is different between SoCs,
74 #define IMX_I2C_IADR 0x00 /* i2c slave address */
75 #define IMX_I2C_IFDR 0x01 /* i2c frequency divider */
76 #define IMX_I2C_I2CR 0x02 /* i2c control */
77 #define IMX_I2C_I2SR 0x03 /* i2c status */
78 #define IMX_I2C_I2DR 0x04 /* i2c transfer data */
83 #define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */
89 /* Bits of IMX I2C registers */
108 * - write zero to clear(w0c) INT flag on i.MX,
109 * - but write one to clear(w1c) INT flag on Vybrid.
110 * 2) I2CR: I2C module enable operation also differ between SoCs:
111 * - set I2CR_IEN bit enable the module on i.MX,
112 * - but clear I2CR_IEN bit enable the module on Vybrid.
123 * taken from table 26-5, p.26-9, Freescale i.MX
209 * I2C: When the I2C clock speed is configured for 400 kHz,
210 * the SCL low period violates the I2C spec of 1.3 uS min.
319 .name = "imx1-i2c",
322 .name = "imx21-i2c",
331 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, },
332 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, },
333 { .compatible = "fsl,imx6q-i2c", .data = &imx6_i2c_hwdata, },
334 { .compatible = "fsl,imx6sl-i2c", .data = &imx6_i2c_hwdata, },
335 { .compatible = "fsl,imx6sll-i2c", .data = &imx6_i2c_hwdata, },
336 { .compatible = "fsl,imx6sx-i2c", .data = &imx6_i2c_hwdata, },
337 { .compatible = "fsl,imx6ul-i2c", .data = &imx6_i2c_hwdata, },
338 { .compatible = "fsl,imx7d-i2c", .data = &imx6_i2c_hwdata, },
339 { .compatible = "fsl,imx7s-i2c", .data = &imx6_i2c_hwdata, },
340 { .compatible = "fsl,imx8mm-i2c", .data = &imx6_i2c_hwdata, },
341 { .compatible = "fsl,imx8mn-i2c", .data = &imx6_i2c_hwdata, },
342 { .compatible = "fsl,imx8mp-i2c", .data = &imx6_i2c_hwdata, },
343 { .compatible = "fsl,imx8mq-i2c", .data = &imx6_i2c_hwdata, },
344 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, },
345 { .compatible = "nxp,s32g2-i2c", .data = &s32g2_i2c_hwdata, },
358 return i2c_imx->hwdata->devtype == IMX1_I2C;
363 return i2c_imx->hwdata->devtype == VF610_I2C;
369 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
375 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
387 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
391 /* Set up i2c controller register and i2c status register to default value. */
394 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
404 struct device *dev = i2c_imx->adapter.dev.parent;
409 return -ENOMEM;
411 dma->chan_tx = dma_request_chan(dev, "tx");
412 if (IS_ERR(dma->chan_tx)) {
413 ret = PTR_ERR(dma->chan_tx);
414 if (ret != -ENODEV && ret != -EPROBE_DEFER)
420 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
424 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
430 dma->chan_rx = dma_request_chan(dev, "rx");
431 if (IS_ERR(dma->chan_rx)) {
432 ret = PTR_ERR(dma->chan_rx);
433 if (ret != -ENODEV && ret != -EPROBE_DEFER)
439 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
443 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
449 i2c_imx->dma = dma;
450 init_completion(&dma->cmd_complete);
452 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
457 dma_release_channel(dma->chan_rx);
459 dma_release_channel(dma->chan_tx);
469 struct imx_i2c_dma *dma = i2c_imx->dma;
471 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
472 dma->dma_len, dma->dma_data_dir);
473 complete(&dma->cmd_complete);
479 struct imx_i2c_dma *dma = i2c_imx->dma;
481 struct device *dev = &i2c_imx->adapter.dev;
482 struct device *chan_dev = dma->chan_using->device->dev;
484 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
485 dma->dma_len, dma->dma_data_dir);
486 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
491 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
492 dma->dma_len, dma->dma_transfer_dir,
499 reinit_completion(&dma->cmd_complete);
500 txdesc->callback = i2c_imx_dma_callback;
501 txdesc->callback_param = i2c_imx;
507 dma_async_issue_pending(dma->chan_using);
511 dmaengine_terminate_sync(dma->chan_using);
513 dma_unmap_single(chan_dev, dma->dma_buf,
514 dma->dma_len, dma->dma_data_dir);
516 return -EINVAL;
521 struct imx_i2c_dma *dma = i2c_imx->dma;
523 dma->dma_buf = 0;
524 dma->dma_len = 0;
526 dma_release_channel(dma->chan_tx);
527 dma->chan_tx = NULL;
529 dma_release_channel(dma->chan_rx);
530 dma->chan_rx = NULL;
532 dma->chan_using = NULL;
537 bool multi_master = i2c_imx->multi_master;
547 return -EAGAIN;
551 i2c_imx->stopped = 0;
555 i2c_imx->stopped = 1;
559 dev_dbg(&i2c_imx->adapter.dev,
560 "<%s> I2C bus is busy\n", __func__);
561 return -ETIMEDOUT;
575 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift);
579 * The formula for the poll timeout is documented in the RM
582 * Set the value hard as it is done for the non-atomic use-case.
584 * allowed SMBus frequency. Also add an offset of 100us since it
586 * the minimum timeout in polling mode.
589 i2c_imx->i2csr = regval;
592 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10);
595 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
596 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
597 return -ETIMEDOUT;
600 /* In multi-master mode check for arbitration lost */
601 if (i2c_imx->multi_master && (i2c_imx->i2csr & I2SR_IAL)) {
602 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__);
605 i2c_imx->i2csr = 0;
606 return -EAGAIN;
609 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
610 i2c_imx->i2csr = 0;
617 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
618 return -ENXIO; /* No ACK */
621 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
628 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div;
632 if (i2c_imx->hwdata->has_err007805 && i2c_imx->bitrate > 384000) {
633 dev_dbg(&i2c_imx->adapter.dev,
635 i2c_imx->bitrate);
636 i2c_imx->bitrate = 384000;
640 if (i2c_imx->cur_clk == i2c_clk_rate)
645 return -EINVAL;
647 i2c_imx->cur_clk = i2c_clk_rate;
649 div = DIV_ROUND_UP(i2c_clk_rate, i2c_imx->bitrate);
652 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div)
653 i = i2c_imx->hwdata->ndivs - 1;
659 i2c_imx->ifdr = i2c_clk_div[i].val;
663 * It should be about one I2C clock period long.
664 * This delay is used in I2C bus disable function
667 i2c_imx->disable_delay = DIV_ROUND_UP(500000U * i2c_clk_div[i].div,
671 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n",
673 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n",
690 ret = i2c_imx_set_clk(i2c_imx, ndata->new_rate);
700 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR);
701 /* Enable I2C controller */
702 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
703 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR);
711 /* Start I2C transaction */
732 if (!i2c_imx->stopped) {
733 /* Stop I2C transaction */
736 i2c_imx->stopped = 1;
738 if (i2c_imx->dma)
747 udelay(i2c_imx->disable_delay);
750 if (!i2c_imx->stopped)
753 /* Disable I2C controller */
754 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN;
760 * Note: IBIC register will be cleared after disabled i2c module.
777 i2c_slave_event(i2c_imx->slave, event, val);
778 i2c_imx->last_slave_event = event;
785 while (i2c_imx->last_slave_event != I2C_SLAVE_STOP) {
786 switch (i2c_imx->last_slave_event) {
823 /* Data transfer still in progress, ignore this. */
828 if (status & I2SR_SRW) { /* Master wants to read from us*/
829 dev_dbg(&i2c_imx->adapter.dev, "read requested");
839 } else { /* Master wants to write to us */
840 dev_dbg(&i2c_imx->adapter.dev, "write requested");
878 * 1, then everything is fine. If it returns -1, then the
883 hrtimer_try_to_cancel(&i2c_imx->slave_timer);
884 hrtimer_forward_now(&i2c_imx->slave_timer, I2C_IMX_CHECK_DELAY);
885 hrtimer_restart(&i2c_imx->slave_timer);
896 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
900 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
909 imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
914 temp = i2c_imx->hwdata->i2cr_ien_opcode;
917 /* Enable interrupt from i2c module */
926 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
929 if (i2c_imx->slave)
930 return -EBUSY;
932 i2c_imx->slave = client;
933 i2c_imx->last_slave_event = I2C_SLAVE_STOP;
936 ret = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
938 dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
949 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
952 if (!i2c_imx->slave)
953 return -EINVAL;
960 i2c_imx->slave = NULL;
963 ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
965 dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
972 i2c_imx->isr_result = 0;
975 i2c_imx->state = IMX_I2C_STATE_FAILED;
976 i2c_imx->isr_result = -ENXIO;
977 wake_up(&i2c_imx->queue);
980 return i2c_imx->isr_result;
991 if (i2c_imx->msg->len == i2c_imx->msg_buf_idx)
994 imx_i2c_write_reg(i2c_imx->msg->buf[i2c_imx->msg_buf_idx++], i2c_imx, IMX_I2C_I2DR);
1011 if (i2c_imx->msg->len - 1)
1024 if ((i2c_imx->msg->len - 1) == i2c_imx->msg_buf_idx) {
1025 if (i2c_imx->is_lastmsg) {
1032 i2c_imx->stopped = 1;
1037 * For i2c master receiver repeat restart operation like:
1038 * read -> repeat MSTA -> read/write
1047 } else if (i2c_imx->msg_buf_idx == (i2c_imx->msg->len - 2)) {
1053 i2c_imx->msg->buf[i2c_imx->msg_buf_idx++] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1061 i2c_imx->isr_result = -EPROTO;
1062 i2c_imx->state = IMX_I2C_STATE_FAILED;
1063 wake_up(&i2c_imx->queue);
1065 i2c_imx->msg->len += len;
1071 * This state machine handles I2C reception and transmission in non-DMA
1074 * the ISR, SMBus devices may timeout, leading to a bus error.
1076 switch (i2c_imx->state) {
1078 i2c_imx->i2csr = status;
1079 wake_up(&i2c_imx->queue);
1085 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE;
1090 if (i2c_imx->msg_buf_idx == i2c_imx->msg->len) {
1091 i2c_imx->state = IMX_I2C_STATE_DONE;
1092 wake_up(&i2c_imx->queue);
1099 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA_LEN;
1104 i2c_imx->state = IMX_I2C_STATE_READ_CONTINUE;
1110 i2c_imx->state = IMX_I2C_STATE_DONE;
1111 wake_up(&i2c_imx->queue);
1115 i2c_imx->i2csr = status;
1116 i2c_imx->state = IMX_I2C_STATE_FAILED;
1117 i2c_imx->isr_result = -EINVAL;
1118 wake_up(&i2c_imx->queue);
1130 spin_lock_irqsave(&i2c_imx->slave_lock, flags);
1136 if (i2c_imx->slave) {
1142 spin_unlock_irqrestore(&i2c_imx->slave_lock,
1148 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
1151 spin_unlock_irqrestore(&i2c_imx->slave_lock, flags);
1163 struct imx_i2c_dma *dma = i2c_imx->dma;
1164 struct device *dev = &i2c_imx->adapter.dev;
1166 i2c_imx->state = IMX_I2C_STATE_DMA;
1168 dma->chan_using = dma->chan_tx;
1169 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
1170 dma->dma_data_dir = DMA_TO_DEVICE;
1171 dma->dma_len = msgs->len - 1;
1186 &i2c_imx->dma->cmd_complete,
1189 dmaengine_terminate_sync(dma->chan_using);
1190 return -ETIMEDOUT;
1193 /* Waiting for transfer complete. */
1200 dev_dbg(dev, "<%s> Timeout\n", __func__);
1201 return -ETIMEDOUT;
1211 imx_i2c_write_reg(msgs->buf[msgs->len-1],
1235 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
1245 if (msgs->len - 1)
1263 struct imx_i2c_dma *dma = i2c_imx->dma;
1264 struct device *dev = &i2c_imx->adapter.dev;
1266 i2c_imx->state = IMX_I2C_STATE_DMA;
1272 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1274 dma->chan_using = dma->chan_rx;
1275 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
1276 dma->dma_data_dir = DMA_FROM_DEVICE;
1278 dma->dma_len = msgs->len - 2;
1284 &i2c_imx->dma->cmd_complete,
1287 dmaengine_terminate_sync(dma->chan_using);
1288 return -ETIMEDOUT;
1291 /* waiting for transfer complete. */
1298 dev_dbg(dev, "<%s> Timeout\n", __func__);
1299 return -ETIMEDOUT;
1308 /* read n-1 byte data */
1313 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1327 i2c_imx->stopped = 1;
1330 if (!i2c_imx->stopped)
1334 * For i2c master receiver repeat restart operation like:
1335 * read -> repeat MSTA -> read/write
1344 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1354 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1365 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
1368 for (i = 0; i < msgs->len; i++) {
1369 dev_dbg(&i2c_imx->adapter.dev,
1371 __func__, i, msgs->buf[i]);
1372 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR);
1385 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
1388 i2c_imx->state = IMX_I2C_STATE_WRITE;
1389 i2c_imx->msg = msgs;
1390 i2c_imx->msg_buf_idx = 0;
1397 wait_event_timeout(i2c_imx->queue,
1398 i2c_imx->state == IMX_I2C_STATE_DONE ||
1399 i2c_imx->state == IMX_I2C_STATE_FAILED,
1400 (msgs->len + 1) * HZ / 10);
1401 if (i2c_imx->state == IMX_I2C_STATE_FAILED) {
1402 dev_dbg(&i2c_imx->adapter.dev, "<%s> write failed with %d\n",
1403 __func__, i2c_imx->isr_result);
1404 return i2c_imx->isr_result;
1406 if (i2c_imx->state != IMX_I2C_STATE_DONE) {
1407 dev_err(&i2c_imx->adapter.dev, "<%s> write timedout\n", __func__);
1408 return -ETIMEDOUT;
1418 int block_data = msgs->flags & I2C_M_RECV_LEN;
1424 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
1427 for (i = 0; i < msgs->len; i++) {
1436 * msgs->len.
1441 return -EPROTO;
1442 dev_dbg(&i2c_imx->adapter.dev,
1445 msgs->len += len;
1447 if (i == (msgs->len - 1)) {
1453 dev_dbg(&i2c_imx->adapter.dev,
1457 i2c_imx->stopped = 1;
1460 if (!i2c_imx->stopped)
1464 * For i2c master receiver repeat restart operation like:
1465 * read -> repeat MSTA -> read/write
1474 } else if (i == (msgs->len - 2)) {
1475 dev_dbg(&i2c_imx->adapter.dev,
1482 msgs->buf[0] = len;
1484 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
1485 dev_dbg(&i2c_imx->adapter.dev,
1487 __func__, i, msgs->buf[i]);
1495 int block_data = msgs->flags & I2C_M_RECV_LEN;
1497 dev_dbg(&i2c_imx->adapter.dev,
1501 i2c_imx->is_lastmsg = is_lastmsg;
1504 i2c_imx->state = IMX_I2C_STATE_READ_BLOCK_DATA;
1506 i2c_imx->state = IMX_I2C_STATE_READ;
1507 i2c_imx->msg = msgs;
1508 i2c_imx->msg_buf_idx = 0;
1515 wait_event_timeout(i2c_imx->queue,
1516 i2c_imx->state == IMX_I2C_STATE_DONE ||
1517 i2c_imx->state == IMX_I2C_STATE_FAILED,
1518 (msgs->len + 1) * HZ / 10);
1519 if (i2c_imx->state == IMX_I2C_STATE_FAILED) {
1520 dev_dbg(&i2c_imx->adapter.dev, "<%s> read failed with %d\n",
1521 __func__, i2c_imx->isr_result);
1522 return i2c_imx->isr_result;
1524 if (i2c_imx->state != IMX_I2C_STATE_DONE) {
1525 dev_err(&i2c_imx->adapter.dev, "<%s> read timedout\n", __func__);
1526 return -ETIMEDOUT;
1528 if (!i2c_imx->stopped)
1543 /* Start I2C transfer */
1550 if (!atomic && i2c_imx->adapter.bus_recovery_info) {
1551 i2c_recover_bus(&i2c_imx->adapter);
1561 if (i == num - 1)
1565 dev_dbg(&i2c_imx->adapter.dev,
1574 dev_dbg(&i2c_imx->adapter.dev,
1575 "<%s> transfer message: %d\n", __func__, i);
1579 dev_dbg(&i2c_imx->adapter.dev,
1586 dev_dbg(&i2c_imx->adapter.dev,
1595 use_dma = i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD &&
1598 int block_data = msgs->flags & I2C_M_RECV_LEN;
1619 /* Stop I2C transfer */
1622 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
1626 if (i2c_imx->slave)
1638 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent);
1644 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent);
1645 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent);
1656 result = clk_enable(i2c_imx->clk);
1662 clk_disable(i2c_imx->clk);
1677 struct i2c_bus_recovery_info *bri = &i2c_imx->rinfo;
1679 bri->pinctrl = devm_pinctrl_get(&pdev->dev);
1680 if (IS_ERR(bri->pinctrl))
1681 return PTR_ERR(bri->pinctrl);
1683 i2c_imx->adapter.bus_recovery_info = bri;
1706 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
1720 phy_addr = (dma_addr_t)res->start;
1721 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
1723 return -ENOMEM;
1725 spin_lock_init(&i2c_imx->slave_lock);
1726 hrtimer_setup(&i2c_imx->slave_timer, i2c_imx_slave_timeout, CLOCK_MONOTONIC,
1729 match = device_get_match_data(&pdev->dev);
1731 i2c_imx->hwdata = match;
1733 i2c_imx->hwdata = (struct imx_i2c_hwdata *)
1734 platform_get_device_id(pdev)->driver_data;
1737 strscpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name));
1738 i2c_imx->adapter.owner = THIS_MODULE;
1739 i2c_imx->adapter.algo = &i2c_imx_algo;
1740 i2c_imx->adapter.dev.parent = &pdev->dev;
1741 i2c_imx->adapter.nr = pdev->id;
1742 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
1743 i2c_imx->base = base;
1744 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev));
1746 /* Get I2C clock */
1747 i2c_imx->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1748 if (IS_ERR(i2c_imx->clk))
1749 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk),
1750 "can't get I2C clock\n");
1753 init_waitqueue_head(&i2c_imx->queue);
1756 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
1761 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT);
1762 pm_runtime_use_autosuspend(&pdev->dev);
1763 pm_runtime_set_active(&pdev->dev);
1764 pm_runtime_enable(&pdev->dev);
1766 ret = pm_runtime_get_sync(&pdev->dev);
1772 pdev->name, i2c_imx);
1774 dev_err(&pdev->dev, "can't claim irq %d\n", irq);
1779 * We use the single-master property for backward compatibility.
1782 i2c_imx->multi_master = !of_property_read_bool(pdev->dev.of_node, "single-master");
1785 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ;
1786 ret = of_property_read_u32(pdev->dev.of_node,
1787 "clock-frequency", &i2c_imx->bitrate);
1788 if (ret < 0 && pdata && pdata->bitrate)
1789 i2c_imx->bitrate = pdata->bitrate;
1790 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call;
1791 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
1792 ret = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
1794 dev_err(&pdev->dev, "can't get I2C clock\n");
1803 if (ret == -EPROBE_DEFER)
1807 * DMA mode should be optional for I2C, when encountering DMA errors,
1808 * no need to exit I2C probe. Only print warning to show DMA error and
1809 * use PIO mode directly to ensure I2C bus available as much as possible.
1813 if (ret == -EPROBE_DEFER)
1815 else if (ret == -ENODEV)
1816 dev_dbg(&pdev->dev, "Only use PIO mode\n");
1818 dev_warn(&pdev->dev, "Failed to setup DMA (%pe), only use PIO mode\n",
1822 /* Add I2C adapter */
1823 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
1827 pm_runtime_mark_last_busy(&pdev->dev);
1828 pm_runtime_put_autosuspend(&pdev->dev);
1830 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq);
1831 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res);
1832 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
1833 i2c_imx->adapter.name);
1834 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
1839 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1842 pm_runtime_put_noidle(&pdev->dev);
1843 pm_runtime_disable(&pdev->dev);
1844 pm_runtime_set_suspended(&pdev->dev);
1845 pm_runtime_dont_use_autosuspend(&pdev->dev);
1854 ret = pm_runtime_get_sync(&pdev->dev);
1856 hrtimer_cancel(&i2c_imx->slave_timer);
1859 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
1860 i2c_del_adapter(&i2c_imx->adapter);
1862 if (i2c_imx->dma)
1873 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb);
1878 pm_runtime_put_noidle(&pdev->dev);
1879 pm_runtime_disable(&pdev->dev);
1886 clk_disable(i2c_imx->clk);
1899 ret = clk_enable(i2c_imx->clk);
1901 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret);
1909 * Some I2C devices may need the I2C controller to remain active
1914 * During system resume, the I2C controller will be available only
1915 * after runtime PM is re-enabled (in resume_early()). However, this
1919 * is still enabled. The I2C controller will remain available until
1921 * called. During resume, the I2C controller can be restored by the
1924 * Finally, the resume() callback re-enables autosuspend, ensuring
1925 * the I2C controller remains available until the system enters
1972 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");