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/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-pxa.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MMP I2C controller
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
17 - mrvl,i2c-polling
20 - interrupts
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H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
11 title: NVIDIA Tegra I2C controller driver
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
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H A Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C controller embedded in STMicroelectronics STM32 I2C platform
10 - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp13-i2c
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H A Di2c-rk3x.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-rk3x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3xxx I2C controller
10 This driver interfaces with the native I2C controller present in Rockchip
14 - $ref: /schemas/i2c/i2c-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rv1108-i2c
24 - const: rockchip,rk3066-i2c
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/linux/drivers/i2c/busses/
H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/i2c.h>
25 /* I2C register address definitions */
35 /* I2C register bit definitions */
56 #define SYNQUACER_I2C_CCR_FM BIT(6) // Speed Mode Select
68 /* STANDARD MODE frequency */
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
71 /* FAST MODE frequency */
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
76 /* calculate the value of CS bits in CCR register on standard mode */
[all …]
H A Di2c-tegra.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
14 #include <linux/dma-mapping.h>
16 #include <linux/i2c.h>
51 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
52 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
130 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
131 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
144 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
154 * @MSG_END_REPEAT_START: Send repeat-start.
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H A Di2c-designware-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
15 #include <linux/i2c.h>
192 * struct dw_i2c_dev - private i2c-designware data
202 * @slave: represent an I2C slave device
214 * @status: i2c master status, one of STATUS_*
216 * @sw_mask: SW mask of DW_IC_INTR_MASK used in polling mode
217 * @irq: interrupt number for the i2c master
219 * @adapter: i2c subsystem adapter node
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H A Di2c-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale MXS I2C bus driver
5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K.
8 * based on a (non-working) driver which was:
10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
16 #include <linux/i2c.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/dma/mxs-dma.h>
29 #define DRIVER_NAME "mxs-i2c"
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H A Di2c-jz4780.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 I2C bus driver
5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
15 #include <linux/i2c.h>
113 #define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
114 #define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
115 #define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
116 #define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
171 static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c, in jz4780_i2c_readw() argument
174 return readw(i2c->iomem + offset); in jz4780_i2c_readw()
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H A Di2c-stm32f7.c1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
14 * This driver is based on i2c-stm32f4.c
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
38 #include "i2c-stm32.h"
40 /* STM32F7 I2C registers */
52 /* STM32F7 I2C control 1 */
84 /* STM32F7 I2C control 2 */
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H A Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
6 * I2C master mode controller driver, used in Nomadik 8815
11 * - The memory bus only supports 32-bit accesses.
12 * - (only EyeQ5) A register must be configured for the I2C speed mode;
22 #include <linux/i2c.h>
35 #define DRIVER_NAME "nmk-i2c"
37 /* I2C Controller register offsets */
56 #define I2C_CR_OM GENMASK(2, 1) /* Operating mode */
57 #define I2C_CR_SAM BIT(3) /* Slave addressing mode */
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H A Di2c-designware-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
21 #include <linux/i2c.h>
35 #include "i2c-designware-core.h"
39 "slave address not acknowledged (7bit mode)",
41 "first address byte not acknowledged (10bit mode)",
43 "second address byte not acknowledged (10bit mode)",
55 "trying to read when restart is disabled (10bit mode)",
65 "incorrect slave-transmitter mode configuration",
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/linux/Documentation/devicetree/bindings/power/supply/
H A Drichtek,rt5033-charger.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/richtek,rt5033-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jakob Hauser <jahau@rocketmail.com>
14 under sub-node named "charger" using the following format.
18 const: richtek,rt5033-charger
20 monitored-battery:
26 precharge-current-microamp:
27 Current of pre-charge mode. The pre-charge current levels are 350 mA
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/linux/include/linux/
H A Di2c-algo-pca.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #define I2C_PCA_OSC_PER 3 /* e10-8s */
34 #define I2C_PCA_ICOUNT 0x00 /* Byte Count for buffered mode */
40 #define I2C_PCA_IMODE 0x06 /* I2C Bus mode */
42 /* PCA9665 I2C bus mode */
43 #define I2C_PCA_MODE_STD 0x00 /* Standard mode */
44 #define I2C_PCA_MODE_FAST 0x01 /* Fast mode */
45 #define I2C_PCA_MODE_FASTP 0x02 /* Fast Plus mode */
46 #define I2C_PCA_MODE_TURBO 0x03 /* Turbo mode */
57 * struct pca_i2c_bus_settings - The configured PCA i2c bus settings
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H A Di2c-algo-bit.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * i2c-algo-bit.h: i2c driver algorithms for bit-shift adapters
5 * Copyright (C) 1995-99 Simon G. Vogl
13 #include <linux/i2c.h>
15 /* --- Defines for bit-adapters --------------------------------------- */
17 * This struct contains the hw-dependent functions of bit-style adapters to
18 * manipulate the line states, and to init any hw-specific features. This is
19 * only used if you have more than one hw-type of adapter running.
32 minimum 2 us for fast-mode I2C,
33 minimum 5 us for standard-mode I2C and SMBus,
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-inventec-starscream.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include "aspeed-g6-pinctrl.dtsi"
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/gpio/aspeed-gpio.h>
13 compatible = "inventec,starscream-bmc", "aspeed,ast2600";
20 stdout-path = &uart5;
28 reserved-memory {
29 #address-cells = <1>;
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H A Daspeed-bmc-inventec-transformers.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include "aspeed-g6-pinctrl.dtsi"
8 #include <dt-bindings/i2c/i2c.h>
9 #include <dt-bindings/gpio/aspeed-gpio.h>
13 compatible = "inventec,transformer-bmc", "aspeed,ast2600";
20 stdout-path = &uart5;
30 compatible = "gpio-leds";
49 ethphy0: ethernet-phy@0 {
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/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrx_dap_fasi.h2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
36 * Data access protocol: Fast Access Sequential Interface (fasi)
37 * Fast access, because of short addressing format (16 instead of 32 bits addr)
38 * Sequential, because of I2C.
48 /*-------- compilation control switches --------------------------------------*/
53 /*-------- Required includes -------------------------------------------------*/
57 /*-------- Defines, configuring the API --------------------------------------*/
98 #error At least one of short- or long-addressing format must be allowed.
112 * + single master mode means no use of repeated starts
113 * + multi master mode means use of repeated starts
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/linux/drivers/usb/misc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
13 Technologies USS-720 chip. These cables are plugged into your USB
17 The chip has two modes: automatic mode and manual mode. In automatic
18 mode, it looks to the computer like a standard USB printer. Only
19 printers may be connected to the USS-720 in this mode. The generic
21 that mode, and you can say N here if you want to use the chip only
22 in this mode.
24 Manual mode is not limited to printers, any parallel port
25 device should work. This driver utilizes manual mode.
30 Say Y here if you own an USS-720 USB->Parport cable and intend to
[all …]
/linux/sound/soc/codecs/
H A Dlm4857.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright 2011 Lars-Peter Clausen <lars@metafoo.de>
13 #include <linux/i2c.h>
59 SOC_DAPM_ENUM("Mode", lm4857_mode_enum);
64 SND_SOC_DAPM_DEMUX("Mode", SND_SOC_NOPM, 0, 0, &lm4857_mode_ctrl),
71 static const DECLARE_TLV_DB_SCALE(stereo_tlv, -4050, 150, 0);
72 static const DECLARE_TLV_DB_SCALE(mono_tlv, -3450, 150, 0);
83 SOC_SINGLE("Fast Wakeup Playback Switch", LM4857_CTRL,
90 { "Mode", NULL, "IN" },
91 { "LS", "Loudspeaker", "Mode" },
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dbrcm,bcm11351-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <florian.fainelli@broadcom.com>
11 - Ray Jui <rjui@broadcom.com>
12 - Scott Branden <sbranden@broadcom.com>
15 - $ref: pinctrl.yaml#
19 const: brcm,bcm11351-pinctrl
25 '-pins$':
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-3720-uDPU.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "armada-3720-uDPU.dtsi"
11 sfp_eth0: sfp-eth0 {
13 i2c-bus = <&i2c0>;
14 los-gpios = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
15 mod-def0-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
16 tx-disable-gpios = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
17 tx-fault-gpios = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
18 maximum-power-milliwatt = <3000>;
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/linux/Documentation/devicetree/bindings/clock/
H A Dnvidia,tegra124-dfll.txt4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
[all …]
/linux/Documentation/devicetree/bindings/i3c/
H A Di3c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Miquel Raynal <miquel.raynal@bootlin.com>
15 and a set of child nodes for each I2C or I3C slave on the bus. Each of them
20 pattern: "^i3c@[0-9a-f]+$"
22 "#address-cells":
25 Each I2C device connected to the bus should be described in a subnode.
35 this I3C device has a static I2C address and we want to assign it a
[all …]

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