Lines Matching +full:i2c +full:- +full:fast +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver.
5 * Based on the TI DAVINCI I2C adapter driver.
21 #include <linux/i2c.h>
35 #include "i2c-designware-core.h"
39 "slave address not acknowledged (7bit mode)",
41 "first address byte not acknowledged (10bit mode)",
43 "second address byte not acknowledged (10bit mode)",
55 "trying to read when restart is disabled (10bit mode)",
65 "incorrect slave-transmitter mode configuration",
72 *val = readl(dev->base + reg); in dw_reg_read()
81 writel(val, dev->base + reg); in dw_reg_write()
90 *val = swab32(readl(dev->base + reg)); in dw_reg_read_swab()
99 writel(swab32(val), dev->base + reg); in dw_reg_write_swab()
108 *val = readw(dev->base + reg) | in dw_reg_read_word()
109 (readw(dev->base + reg + 2) << 16); in dw_reg_read_word()
118 writew(val, dev->base + reg); in dw_reg_write_word()
119 writew(val >> 16, dev->base + reg + 2); in dw_reg_write_word()
125 * i2c_dw_init_regmap() - Initialize registers map
128 * Autodetects needed register access mode and creates the regmap with
152 if (dev->map) in i2c_dw_init_regmap()
159 reg = readl(dev->base + DW_IC_COMP_TYPE); in i2c_dw_init_regmap()
162 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU) in i2c_dw_init_regmap()
172 dev_err(dev->dev, in i2c_dw_init_regmap()
174 return -ENODEV; in i2c_dw_init_regmap()
180 * basically we have MMIO-based regmap, so none of the read/write methods in i2c_dw_init_regmap()
183 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg); in i2c_dw_init_regmap()
184 if (IS_ERR(dev->map)) { in i2c_dw_init_regmap()
185 dev_err(dev->dev, "Failed to init the registers map\n"); in i2c_dw_init_regmap()
186 return PTR_ERR(dev->map); in i2c_dw_init_regmap()
201 struct i2c_timings *t = &dev->timings; in i2c_dw_validate_speed()
205 * Only standard mode at 100kHz, fast mode at 400kHz, in i2c_dw_validate_speed()
206 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported. in i2c_dw_validate_speed()
209 if (t->bus_freq_hz == supported_speeds[i]) in i2c_dw_validate_speed()
213 dev_err(dev->dev, in i2c_dw_validate_speed()
215 t->bus_freq_hz); in i2c_dw_validate_speed()
217 return -EINVAL; in i2c_dw_validate_speed()
230 writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE, in mscc_twi_set_sda_hold_time()
231 dev->ext + MSCC_ICPU_CFG_TWI_DELAY); in mscc_twi_set_sda_hold_time()
241 switch (dev->flags & MODEL_MASK) { in i2c_dw_of_configure()
243 dev->ext = devm_platform_ioremap_resource(pdev, 1); in i2c_dw_of_configure()
244 if (!IS_ERR(dev->ext)) in i2c_dw_of_configure()
245 dev->set_sda_hold_time = mscc_twi_set_sda_hold_time; in i2c_dw_of_configure()
292 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) { in i2c_dw_acpi_params()
293 const union acpi_object *objs = obj->package.elements; in i2c_dw_acpi_params()
306 struct i2c_timings *t = &dev->timings; in i2c_dw_acpi_configure()
313 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht); in i2c_dw_acpi_configure()
314 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht); in i2c_dw_acpi_configure()
315 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht); in i2c_dw_acpi_configure()
316 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht); in i2c_dw_acpi_configure()
318 switch (t->bus_freq_hz) { in i2c_dw_acpi_configure()
320 dev->sda_hold_time = ss_ht; in i2c_dw_acpi_configure()
323 dev->sda_hold_time = fp_ht; in i2c_dw_acpi_configure()
326 dev->sda_hold_time = hs_ht; in i2c_dw_acpi_configure()
330 dev->sda_hold_time = fs_ht; in i2c_dw_acpi_configure()
363 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev); in i2c_dw_adjust_bus_speed()
364 struct i2c_timings *t = &dev->timings; in i2c_dw_adjust_bus_speed()
367 * Find bus speed from the "clock-frequency" device property, ACPI in i2c_dw_adjust_bus_speed()
368 * or by using fast mode if neither is set. in i2c_dw_adjust_bus_speed()
370 if (acpi_speed && t->bus_freq_hz) in i2c_dw_adjust_bus_speed()
371 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed); in i2c_dw_adjust_bus_speed()
372 else if (acpi_speed || t->bus_freq_hz) in i2c_dw_adjust_bus_speed()
373 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed); in i2c_dw_adjust_bus_speed()
375 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; in i2c_dw_adjust_bus_speed()
380 struct i2c_timings *t = &dev->timings; in i2c_dw_fw_parse_and_configure()
381 struct device *device = dev->dev; in i2c_dw_fw_parse_and_configure()
386 if (device_property_read_u32(device, "snps,bus-capacitance-pf", &dev->bus_capacitance_pF)) in i2c_dw_fw_parse_and_configure()
387 dev->bus_capacitance_pF = 100; in i2c_dw_fw_parse_and_configure()
389 dev->clk_freq_optimized = device_property_read_bool(device, "snps,clk-freq-optimized"); in i2c_dw_fw_parse_and_configure()
411 ret = regmap_read(dev->map, reg, &val); in i2c_dw_read_scl_reg()
437 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) - 3 + offset; in i2c_dw_scl_hcnt()
451 * DW I2C core starts counting the SCL CNTs for the LOW period in i2c_dw_scl_lcnt()
457 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 1 + offset; in i2c_dw_scl_lcnt()
470 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®); in i2c_dw_set_sda_hold()
475 if (!dev->sda_hold_time) { in i2c_dw_set_sda_hold()
477 ret = regmap_read(dev->map, DW_IC_SDA_HOLD, in i2c_dw_set_sda_hold()
478 &dev->sda_hold_time); in i2c_dw_set_sda_hold()
484 * Workaround for avoiding TX arbitration lost in case I2C in i2c_dw_set_sda_hold()
486 * SCL by enabling non-zero SDA RX hold. Specification says it in i2c_dw_set_sda_hold()
490 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK)) in i2c_dw_set_sda_hold()
491 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT; in i2c_dw_set_sda_hold()
493 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n", in i2c_dw_set_sda_hold()
494 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK, in i2c_dw_set_sda_hold()
495 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT); in i2c_dw_set_sda_hold()
496 } else if (dev->set_sda_hold_time) { in i2c_dw_set_sda_hold()
497 dev->set_sda_hold_time(dev); in i2c_dw_set_sda_hold()
498 } else if (dev->sda_hold_time) { in i2c_dw_set_sda_hold()
499 dev_warn(dev->dev, in i2c_dw_set_sda_hold()
501 dev->sda_hold_time = 0; in i2c_dw_set_sda_hold()
512 struct i2c_timings *t = &dev->timings; in __i2c_dw_disable()
520 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats); in __i2c_dw_disable()
521 regmap_read(dev->map, DW_IC_STATUS, &ic_stats); in __i2c_dw_disable()
522 regmap_read(dev->map, DW_IC_ENABLE, &enable); in __i2c_dw_disable()
528 regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE); in __i2c_dw_disable()
530 * Wait 10 times the signaling period of the highest I2C in __i2c_dw_disable()
532 * 25us) to ensure the I2C ENABLE bit is already set in __i2c_dw_disable()
533 * as described in the DesignWare I2C databook. in __i2c_dw_disable()
535 fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz)); in __i2c_dw_disable()
540 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT); in __i2c_dw_disable()
541 ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable, in __i2c_dw_disable()
545 dev_err(dev->dev, "timeout while trying to abort current transfer\n"); in __i2c_dw_disable()
554 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status); in __i2c_dw_disable()
559 * Wait 10 times the signaling period of the highest I2C in __i2c_dw_disable()
561 * 25us) as described in the DesignWare I2C databook. in __i2c_dw_disable()
564 } while (timeout--); in __i2c_dw_disable()
566 dev_warn(dev->dev, "timeout in disabling adapter\n"); in __i2c_dw_disable()
575 if (!dev->get_clk_rate_khz) { in i2c_dw_clk_rate()
576 dev_dbg_once(dev->dev, "Callback get_clk_rate_khz() is not defined\n"); in i2c_dw_clk_rate()
579 return dev->get_clk_rate_khz(dev); in i2c_dw_clk_rate()
588 ret = clk_prepare_enable(dev->pclk); in i2c_dw_prepare_clk()
592 ret = clk_prepare_enable(dev->clk); in i2c_dw_prepare_clk()
594 clk_disable_unprepare(dev->pclk); in i2c_dw_prepare_clk()
599 clk_disable_unprepare(dev->clk); in i2c_dw_prepare_clk()
600 clk_disable_unprepare(dev->pclk); in i2c_dw_prepare_clk()
610 if (!dev->acquire_lock) in i2c_dw_acquire_lock()
613 ret = dev->acquire_lock(); in i2c_dw_acquire_lock()
617 dev_err(dev->dev, "couldn't acquire bus ownership\n"); in i2c_dw_acquire_lock()
624 if (dev->release_lock) in i2c_dw_release_lock()
625 dev->release_lock(); in i2c_dw_release_lock()
636 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status, in i2c_dw_wait_bus_not_busy()
640 dev_warn(dev->dev, "timeout waiting for bus ready\n"); in i2c_dw_wait_bus_not_busy()
642 i2c_recover_bus(&dev->adapter); in i2c_dw_wait_bus_not_busy()
644 regmap_read(dev->map, DW_IC_STATUS, &status); in i2c_dw_wait_bus_not_busy()
654 unsigned long abort_source = dev->abort_source; in i2c_dw_handle_tx_abort()
659 dev_dbg(dev->dev, in i2c_dw_handle_tx_abort()
661 return -EREMOTEIO; in i2c_dw_handle_tx_abort()
665 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); in i2c_dw_handle_tx_abort()
668 return -EAGAIN; in i2c_dw_handle_tx_abort()
670 return -EINVAL; /* wrong msgs[] data */ in i2c_dw_handle_tx_abort()
672 return -EIO; in i2c_dw_handle_tx_abort()
682 if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) { in i2c_dw_set_fifo_size()
683 dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH; in i2c_dw_set_fifo_size()
684 dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH; in i2c_dw_set_fifo_size()
697 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m); in i2c_dw_set_fifo_size()
704 if (!dev->tx_fifo_depth) { in i2c_dw_set_fifo_size()
705 dev->tx_fifo_depth = tx_fifo_depth; in i2c_dw_set_fifo_size()
706 dev->rx_fifo_depth = rx_fifo_depth; in i2c_dw_set_fifo_size()
708 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth, in i2c_dw_set_fifo_size()
710 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth, in i2c_dw_set_fifo_size()
721 return dev->functionality; in i2c_dw_func()
738 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_disable()
746 device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev)); in i2c_dw_probe()
748 switch (dev->mode) { in i2c_dw_probe()
754 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode); in i2c_dw_probe()
755 return -EINVAL; in i2c_dw_probe()
765 * I2C operation regions, so tell the PM core and middle layers to in i2c_dw_prepare()
775 if (dev->shared_with_punit) in i2c_dw_runtime_suspend()
788 i2c_mark_adapter_suspended(&dev->adapter); in i2c_dw_suspend()
797 if (!dev->shared_with_punit) in i2c_dw_runtime_resume()
800 dev->init(dev); in i2c_dw_runtime_resume()
810 i2c_mark_adapter_resumed(&dev->adapter); in i2c_dw_resume()
821 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");