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/freebsd/share/man/man4/
H A Dpcm.42 .\" Copyright (c) 2009-2011 Joel Dahl <joel@FreeBSD.org>
39 .Bd -ragged -offset indent
60 driver are: multichannel audio, per-application
61 volume control, dynamic mixing through virtual sound channels, true full
74 .Bl -bullet -compact
118 .Xr snd_uaudio 4 (auto-loaded on device plug)
145 .Bl -tag -width ".Va snd_driver_load" -offset indent
164 To define default values for the different mixer channels,
174 multichannel matrix processor supports up to 18 interleaved channels, but the
175 limit is currently set to 8 channels (as commonly used for 7.1 surround sound).
[all …]
H A Dsnd_uaudio.42 .\" SPDX-License-Identifier: BSD-2-Clause
50 .Cd hw.usb.uaudio.buffer_ms
51 .Cd hw.usb.uaudio.default_bits
52 .Cd hw.usb.uaudio.default_channels
53 .Cd hw.usb.uaudio.default_rate
54 .Cd hw.usb.uaudio.handle_hid
55 .Cd hw.usb.uaudio.debug
62 user-supplied values specified through the
66 "Best" means the configuration with the most channels and highest quality in
85 For a change to take effect during runtime, the device has to be re-attached.
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H A Dsfxge.41 .\" Copyright (c) 2011-2016 Solarflare Communications Inc.
39 .Bd -ragged -offset indent
46 .Bd -literal -offset indent
57 and Receive Side Scaling (RSS) using MSI-X interrupts.
88 .Bl -tag -width indent
89 .It Va hw.sfxge.rx_ring
92 .It Va hw.sfxge.tx_ring
95 .It Va hw.sfxge.tx_dpl_get_max
97 .Dq get-list
98 for queued transmit packets (TCP and non-TCP), used only if the transmit
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/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dqcom_hidma_mgmt.txt7 Each HIDMA HW instance consists of multiple DMA channels. These channels
9 among channels based on the priority and weight assignments.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
34 - max-read-transactions: This value is how many times a read burst is
36 - channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
[all …]
H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-sprd-adi.txt3 ADI is the abbreviation of Anolog-Digital interface, which is used to access
8 ADI controller has 50 channels including 2 software read/write channels and
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
14 triggered by hardware components instead of ADI software channels.
16 Thus we introduce one property named "sprd,hw-channels" to configure hardware
17 channels, the first value specifies the hardware channel id which is used to
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
22 one system is reading/writing data by ADI software channels, that should be under
24 data by ADI software channels at the same time, or two parallel routine of setting
[all …]
H A Dsprd,spi-adi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
20 ADI controller has 50 channels including 2 software read/write channels and
21 48 hardware channels to access analog chip. For 2 software read/write channels,
[all …]
/freebsd/contrib/wpa/src/ap/
H A Dhw_features.c3 * Copyright 2002-2003, Instant802 Networks, Inc.
4 * Copyright 2005-2006, Devicescape Software, Inc.
5 * Copyright (c) 2008-2012, Jouni Malinen <j@w1.fi>
37 os_free(hw_features[i].channels); in hostapd_free_hw_features()
51 switch (chan->flag & HOSTAPD_CHAN_DFS_MASK) { in dfs_info()
68 info[sizeof(info) - 1] = '\0'; in dfs_info()
77 struct hostapd_data *hapd = iface->bss[0]; in hostapd_get_hw_features()
87 return -1; in hostapd_get_hw_features()
95 return -1; in hostapd_get_hw_features()
98 iface->hw_flags = flags; in hostapd_get_hw_features()
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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dqcom-spmi-adc-tm5.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 $ref: thermal-sensor.yaml#
16 - qcom,spmi-adc-tm5
17 - qcom,spmi-adc-tm5-gen2
18 - qcom,adc-tm7 # Incomplete / subject to change
26 "#thermal-sensor-cells":
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H A Dqcom-spmi-adc-tm-hc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/qcom-spmi-adc-tm-hc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 $ref: thermal-sensor.yaml#
15 const: qcom,spmi-adc-tm-hc
23 "#thermal-sensor-cells":
26 "#address-cells":
29 "#size-cells":
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/freebsd/sys/compat/linuxkpi/common/src/
H A Dlinux_80211.c1 /*-
2 * Copyright (c) 2020-2025 The FreeBSD Foundation
3 * Copyright (c) 2020-2025 Bjoern A. Zeeb
37 * for these (e.g., struct hw -> struct lkpi_hw, struct sta -> struct lkpi_sta).
39 * We call the internal versions lxxx (e.g., hw -> lhw, sta -> lsta).
44 * - lots :)
45 * - HW_CRYPTO: we need a "keystore" and an ordered list for suspend/resume.
96 /* XXX-BZ really want this and others in queue.h */
98 (elm)->field.tqe_next = NULL; \
99 (elm)->field.tqe_prev = NULL; \
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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
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/freebsd/sys/contrib/dev/iwlwifi/mvm/
H A Dscan.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
13 #include "iwl-io.h"
14 #include "iwl-utils.h"
33 /* adaptive dwell default APs number in social channels (1, 6, 11) */
35 /* number of scan channels */
39 /* adaptive dwell number of APs override mask for social channels */
41 /* adaptive dwell number of APs override for p2p friendly GO channels */
[all …]
H A Dnvm.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2012-2014, 2018-2019, 2021-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 #include "iwl-trans.h"
12 #include "iwl-csr.h"
14 #include "iwl-nvm-utils.h"
15 #include "iwl-nvm-parse.h"
16 #include "iwl-prph.h"
62 nvm_resp = (void *)pkt->data; in iwl_nvm_write_chunk()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm8450-hdk.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
10 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
11 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
12 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
13 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
24 compatible = "qcom,sm8450-hdk", "qcom,sm8450";
25 chassis-type = "embedded";
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H A Dsm7225-fairphone-fp4.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
15 #include <dt-bindings/firmware/qcom,scm.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
18 #include <dt-bindings/input/input.h>
19 #include <dt-bindings/leds/common.h>
20 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
21 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
22 #include <dt-bindings/usb/pd.h>
[all …]
H A Dsm8250-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/sound/qcom,q6afe.h>
10 #include <dt-bindings/sound/qcom,q6asm.h>
11 #include <dt-bindings/gpio/gpio.h>
20 compatible = "qcom,sm8250-mtp", "qcom,sm8250";
21 chassis-type = "handset";
27 wcd938x: audio-codec {
28 compatible = "qcom,wcd9380-codec";
[all …]
H A Dqcm6490-shift-otter.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
12 #include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
13 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
16 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 /delete-node/ &rmtfs_mem;
28 chassis-type = "handset";
36 #address-cells = <2>;
[all …]
H A Dsm6125-sony-xperia-seine-pdx201.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/gpio-keys.h>
12 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
16 qcom,msm-id = <394 0x10000>; /* sm6125 v1 */
17 qcom,board-id = <34 0>;
21 chassis-type = "handset";
29 #address-cells = <2>;
30 #size-cells = <2>;
[all …]
H A Dqcm6490-fairphone-fp5.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
12 #include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
13 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
14 #include <dt-bindings/leds/common.h>
15 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
16 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 /delete-node/ &rmtfs_mem;
28 chassis-type = "handset";
36 #address-cells = <2>;
[all …]
H A Dsm6125-xiaomi-laurel-sprout.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
17 compatible = "xiaomi,laurel-sprout", "qcom,sm6125";
18 chassis-type = "handset";
21 qcom,msm-id = <394 0>; /* sm6125 v1 */
22 qcom,board-id = <11 0>;
[all …]
H A Dpm660.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/iio/qcom,spmi-vadc.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/spmi/spmi.h>
10 #include <dt-bindings/thermal/thermal.h>
13 thermal-zones {
14 pm660-thermal {
15 polling-delay-passive = <250>;
17 thermal-sensors = <&pm660_temp>;
[all …]
/freebsd/sys/contrib/dev/iwlwifi/mld/
H A Dscan.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2024-2025 Intel Corporation
7 #include "iwl-utils.h"
35 /* adaptive dwell default APs number for P2P social channels (1, 6, 11) */
38 /* adaptive dwell number of APs override for P2P friendly GO channels */
41 /* adaptive dwell number of APs override for P2P social channels */
47 /* adaptive dwell number of APs override mask for social channels */
52 /* minimal number of 2GHz and 5GHz channels in the regular scan request */
98 struct ieee80211_channel **channels; member
130 if (vif == data->current_vif) in iwl_mld_scan_respect_p2p_go_iter()
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dscan.c1 // SPDX-License-Identifier: ISC
9 struct mt76_phy *phy = dev->scan.phy; in mt76_scan_complete()
17 clear_bit(MT76_SCANNING, &phy->state); in mt76_scan_complete()
19 if (dev->scan.chan && phy->main_chandef.chan) in mt76_scan_complete()
20 mt76_set_channel(phy, &phy->main_chandef, false); in mt76_scan_complete()
21 mt76_put_vif_phy_link(phy, dev->scan.vif, dev->scan.mlink); in mt76_scan_complete()
22 memset(&dev->scan, 0, sizeof(dev->scan)); in mt76_scan_complete()
23 ieee80211_scan_completed(phy->hw, &info); in mt76_scan_complete()
28 cancel_delayed_work_sync(&dev->scan_work); in mt76_abort_scan()
35 struct cfg80211_scan_request *req = dev->scan.req; in mt76_scan_send_probe()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/stm32/
H A Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
[all …]

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