Searched +full:hip06 +full:- +full:lpc (Results 1 – 4 of 4) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/ |
| H A D | hisilicon-low-pin-count.txt | 1 Hisilicon Hip06 Low Pin Count device
2 Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which
4 Hip06 is based on arm64 architecture where there is no I/O space. So, the
6 LPC device node.
9 - compatible: value should be as follows:
10 (a) "hisilicon,hip06-lpc"
11 (b) "hisilicon,hip07-lpc"
12 - #address-cells: must be 2 which stick to the ISA/EISA binding doc.
13 - #size-cells: must be 1 which stick to the ISA/EISA binding doc.
14 - reg: base memory range where the LPC register set is mapped.
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| H A D | low-pin-count.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/low-pin-count.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon HiP06 Low Pin Count device
10 - Wei Xu <xuwei5@hisilicon.com>
13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
15 HiP06 is based on arm64 architecture where there is no I/O space. So, the
17 LPC device node.
21 pattern: '^isa@[0-9a-f]+$'
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| /freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
| H A D | hip06.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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| H A D | hip07.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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