1*c66ec88fSEmmanuel VadotHisilicon Hip06 Low Pin Count device 2*c66ec88fSEmmanuel Vadot Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which 3*c66ec88fSEmmanuel Vadot provides I/O access to some legacy ISA devices. 4*c66ec88fSEmmanuel Vadot Hip06 is based on arm64 architecture where there is no I/O space. So, the 5*c66ec88fSEmmanuel Vadot I/O ports here are not CPU addresses, and there is no 'ranges' property in 6*c66ec88fSEmmanuel Vadot LPC device node. 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel VadotRequired properties: 9*c66ec88fSEmmanuel Vadot- compatible: value should be as follows: 10*c66ec88fSEmmanuel Vadot (a) "hisilicon,hip06-lpc" 11*c66ec88fSEmmanuel Vadot (b) "hisilicon,hip07-lpc" 12*c66ec88fSEmmanuel Vadot- #address-cells: must be 2 which stick to the ISA/EISA binding doc. 13*c66ec88fSEmmanuel Vadot- #size-cells: must be 1 which stick to the ISA/EISA binding doc. 14*c66ec88fSEmmanuel Vadot- reg: base memory range where the LPC register set is mapped. 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel VadotNote: 17*c66ec88fSEmmanuel Vadot The node name before '@' must be "isa" to represent the binding stick to the 18*c66ec88fSEmmanuel Vadot ISA/EISA binding specification. 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel VadotExample: 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel Vadotisa@a01b0000 { 23*c66ec88fSEmmanuel Vadot compatible = "hisilicon,hip06-lpc"; 24*c66ec88fSEmmanuel Vadot #address-cells = <2>; 25*c66ec88fSEmmanuel Vadot #size-cells = <1>; 26*c66ec88fSEmmanuel Vadot reg = <0x0 0xa01b0000 0x0 0x1000>; 27*c66ec88fSEmmanuel Vadot 28*c66ec88fSEmmanuel Vadot ipmi0: bt@e4 { 29*c66ec88fSEmmanuel Vadot compatible = "ipmi-bt"; 30*c66ec88fSEmmanuel Vadot device_type = "ipmi"; 31*c66ec88fSEmmanuel Vadot reg = <0x01 0xe4 0x04>; 32*c66ec88fSEmmanuel Vadot }; 33*c66ec88fSEmmanuel Vadot}; 34