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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_bridge.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include "hdmi.h"
16 static void msm_hdmi_power_on(struct drm_bridge *bridge) in msm_hdmi_power_on() argument
18 struct drm_device *dev = bridge->dev; in msm_hdmi_power_on()
19 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); in msm_hdmi_power_on()
20 struct hdmi *hdmi = hdmi_bridge->hdmi; in msm_hdmi_power_on() local
23 pm_runtime_resume_and_get(&hdmi->pdev->dev); in msm_hdmi_power_on()
25 if (hdmi->extp_clk) { in msm_hdmi_power_on()
26 DBG("pixclock: %lu", hdmi->pixclock); in msm_hdmi_power_on()
27 ret = clk_set_rate(hdmi->extp_clk, hdmi->pixclock); in msm_hdmi_power_on()
[all …]
H A Dhdmi_hpd.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include "hdmi.h"
14 static void msm_hdmi_phy_reset(struct hdmi *hdmi) in msm_hdmi_phy_reset() argument
18 val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); in msm_hdmi_phy_reset()
22 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
26 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
32 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
36 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
44 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
48 hdmi_write(hdmi, REG_HDMI_PHY_CTRL, in msm_hdmi_phy_reset()
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H A Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #include <linux/hdmi.h>
20 #include "hdmi.xml.h"
33 struct hdmi { struct
63 struct drm_bridge *bridge; member
67 /* the encoder we are hooked to (outside of hdmi block) */ argument
98 struct hdmi *hdmi; argument
103 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
105 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data) in hdmi_write() argument
107 writel(data, hdmi->mmio + reg); in hdmi_write()
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H A Dhdmi_audio.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/hdmi.h>
12 #include <sound/hdmi-codec.h>
14 #include "hdmi.h"
16 int msm_hdmi_audio_update(struct hdmi *hdmi) in msm_hdmi_audio_update() argument
18 struct hdmi_audio *audio = &hdmi->audio; in msm_hdmi_audio_update()
19 bool enabled = audio->enabled; in msm_hdmi_audio_update()
23 if (!hdmi->connector->display_info.is_hdmi) in msm_hdmi_audio_update()
24 return -EINVAL; in msm_hdmi_audio_update()
27 audio->enabled, audio->channels, audio->rate); in msm_hdmi_audio_update()
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drk3066_hdmi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Zheng Yang <zhengyang@rock-chips.com>
52 struct drm_bridge bridge; member
63 static struct rk3066_hdmi *bridge_to_rk3066_hdmi(struct drm_bridge *bridge) in bridge_to_rk3066_hdmi() argument
65 return container_of(bridge, struct rk3066_hdmi, bridge); in bridge_to_rk3066_hdmi()
68 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset) in hdmi_readb() argument
70 return readl_relaxed(hdmi->regs + offset); in hdmi_readb()
73 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val) in hdmi_writeb() argument
75 writel_relaxed(val, hdmi->regs + offset); in hdmi_writeb()
78 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset, in hdmi_modb() argument
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/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-qp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
6 * Author: Algea Cao <algea.cao@rock-chips.com>
10 #include <linux/hdmi.h>
19 #include <drm/bridge/dw_hdmi_qp.h>
29 #include <sound/hdmi-codec.h>
31 #include "dw-hdmi-qp.h"
43 * slow so we pre-compute values we expect to see.
46 * the recommended N values specified in the Audio chapter of the HDMI
93 /* For 297 MHz+ HDMI spec have some other rule for setting N */
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H A Ddw-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
13 #include <linux/hdmi.h>
21 #include <linux/dma-mapping.h>
24 #include <media/cec-notifier.h>
26 #include <linux/media-bus-format.h>
29 #include <drm/bridge/dw_hdmi.h>
40 #include "dw-hdmi-audio.h"
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/linux/drivers/gpu/drm/mediatek/
H A Dmtk_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/arm-smccc.h>
10 #include <linux/hdmi.h>
24 #include <sound/hdmi-codec.h>
154 struct drm_bridge bridge; member
180 return container_of(b, struct mtk_hdmi, bridge); in hdmi_ctx_from_bridge()
183 static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black) in mtk_hdmi_hw_vid_black() argument
185 regmap_update_bits(hdmi->regs, VIDEO_CFG_4, in mtk_hdmi_hw_vid_black()
189 static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) in mtk_hdmi_hw_make_reg_writable() argument
194 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI in mtk_hdmi_hw_make_reg_writable()
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/linux/drivers/gpu/drm/meson/
H A Dmeson_encoder_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <media/cec-notifier.h>
29 #include <linux/media-bus-format.h>
40 struct drm_bridge bridge; member
49 container_of(x, struct meson_encoder_hdmi, bridge)
51 static int meson_encoder_hdmi_attach(struct drm_bridge *bridge, in meson_encoder_hdmi_attach() argument
55 struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); in meson_encoder_hdmi_attach()
57 return drm_bridge_attach(encoder, encoder_hdmi->next_bridge, in meson_encoder_hdmi_attach()
58 &encoder_hdmi->bridge, flags); in meson_encoder_hdmi_attach()
61 static void meson_encoder_hdmi_detach(struct drm_bridge *bridge) in meson_encoder_hdmi_detach() argument
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H A Dmeson_dw_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <drm/bridge/dw_hdmi.h>
32 #define DRIVER_NAME "meson-dw-hdmi"
33 #define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
36 * DOC: HDMI Output
38 * HDMI Output is composed of :
40 * - A Synopsys DesignWare HDMI Controller IP
41 * - A TOP control block controlling the Clocks and PHY
42 * - A custom HDMI PHY in order convert video to TMDS signal
47 * | HDMI TOP |<= HPD
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/linux/drivers/gpu/drm/imx/ipuv3/
H A Ddw_hdmi-imx.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
4 * derived from imx-hdmi.c(renamed to bridge/dw_hdmi.c now)
9 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
14 #include <video/imx-ipu-v3.h>
16 #include <drm/bridge/dw_hdmi.h>
25 #include "imx-drm.h"
31 struct imx_hdmi *hdmi; member
36 struct drm_bridge *bridge; member
37 struct dw_hdmi *hdmi; member
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dlontium,lt8912b.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/lontium,lt8912b.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lontium LT8912B MIPI to HDMI Bridge
10 - Adrien Grassein <adrien.grassein@gmail.com>
13 The LT8912B is a bridge device which convert DSI to HDMI
18 - lontium,lt8912b
23 reset-gpios:
32 $ref: /schemas/graph.yaml#/$defs/port-base
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H A Dgoogle,cros-ec-anx7688.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
10 - Nicolas Boichat <drinkcat@chromium.org>
13 ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
14 DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
16 (See google,cros-ec.yaml). It is accessed using I2C tunneling through
18 (See google,cros-ec-i2c-tunnel.yaml).
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H A Dsil,sii8620.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/sil,sii8620.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Image SiI8620 HDMI/MHL bridge
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
22 clock-names:
24 - const: xtal
26 cvcc10-supply:
32 iovcc18-supply:
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H A Dsil,sii9234.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/sil,sii9234.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Silicon Image SiI9234 HDMI/MHL bridge
10 - Maciej Purski <m.purski@samsung.com>
20 avcc12-supply:
23 avcc33-supply:
26 cvcc12-supply:
29 iovcc18-supply:
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H A Dsynopsys,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Synopsys DesignWare HDMI TX Controller
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This document defines device tree properties for the Synopsys DesignWare HDMI
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
26 reg-io-width:
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H A Drenesas,dw-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car DWC HDMI TX Encoder
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: synopsys,dw-hdmi.yaml#
22 - enum:
23 - renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
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/linux/Documentation/gpu/bridge/
H A Ddw-hdmi.rst2 drm/bridge/dw-hdmi Synopsys DesignWare HDMI Controller
5 Synopsys DesignWare HDMI Controller
8 This section covers everything related to the Synopsys DesignWare HDMI
9 Controller implemented as a DRM bridge.
12 -------------------------------------
14 .. kernel-doc:: include/drm/bridge/dw_hdmi.h
/linux/drivers/gpu/drm/bridge/
H A Dtda998x_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/hdmi.h>
15 #include <sound/hdmi-codec.h>
25 #include <media/cec-notifier.h>
27 #include <dt-bindings/display/tda998x.h>
55 struct i2c_client *hdmi; member
83 struct drm_bridge bridge; member
97 container_of(x, struct tda998x_priv, bridge)
411 .addr = priv->cec_addr, in cec_write()
417 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); in cec_write()
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H A Dlontium-lt9611.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019-2020. Linaro Limited.
10 #include <linux/media-bus-format.h>
17 #include <sound/hdmi-codec.h>
39 struct drm_bridge bridge; member
89 static struct lt9611 *bridge_to_lt9611(struct drm_bridge *bridge) in bridge_to_lt9611() argument
91 return container_of(bridge, struct lt9611, bridge); in bridge_to_lt9611()
104 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */ in lt9611_mipi_input_analog()
105 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */ in lt9611_mipi_input_analog()
108 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
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H A Dlontium-lt8912b.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/media-bus-format.h>
31 struct drm_bridge bridge; member
76 /*HDMI Pll Analog*/ in lt8912_write_init_config()
89 return regmap_multi_reg_write(lt->regmap[I2C_MAIN], seq, ARRAY_SIZE(seq)); in lt8912_write_init_config()
102 return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq)); in lt8912_write_mipi_basic_config()
155 return regmap_multi_reg_write(lt->regmap[I2C_CEC_DSI], seq, ARRAY_SIZE(seq)); in lt8912_write_dds_config()
162 ret = regmap_write(lt->regmap[I2C_MAIN], 0x03, 0x7f); in lt8912_write_rxlogicres_config()
164 ret |= regmap_write(lt->regmap[I2C_MAIN], 0x03, 0xff); in lt8912_write_rxlogicres_config()
169 /* enable LVDS output with some hardcoded configuration, not required for the HDMI output */
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H A Dsii902x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Boris Brezillon <boris.brezillon@free-electrons.com>
12 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
16 #include <linux/i2c-mux.h>
18 #include <linux/media-bus-format.h>
31 #include <sound/hdmi-codec.h>
160 (SII902X_TPI_MISC_INFOFRAME_END - SII902X_TPI_MISC_INFOFRAME_BASE)
167 * The maximum resolution supported by the HDMI bridge is 1080p@60Hz
177 struct drm_bridge bridge; member
202 ret = __i2c_smbus_xfer(i2c->adapter, i2c->addr, i2c->flags, in sii902x_read_unlocked()
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H A Dti-tpd12s015.c1 // SPDX-License-Identifier: GPL-2.0
3 * TPD12S015 HDMI ESD protection & level shifter chip driver
7 * Based on the omapdrm-specific encoder-opa362 driver
25 struct drm_bridge bridge; member
35 static inline struct tpd12s015_device *to_tpd12s015(struct drm_bridge *bridge) in to_tpd12s015() argument
37 return container_of(bridge, struct tpd12s015_device, bridge); in to_tpd12s015()
40 static int tpd12s015_attach(struct drm_bridge *bridge, in tpd12s015_attach() argument
44 struct tpd12s015_device *tpd = to_tpd12s015(bridge); in tpd12s015_attach()
48 return -EINVAL; in tpd12s015_attach()
50 ret = drm_bridge_attach(encoder, tpd->next_bridge, in tpd12s015_attach()
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_drv.c1 // SPDX-License-Identifier: GPL-2.0
5 * (C) ST-Ericsson SA 2013
9 * DOC: ST-Ericsson MCDE Driver
11 * The MCDE (short for multi-channel display engine) is a graphics
15 * ST-Ericsson U8500 where is was used for mass-market deployments
18 * It can do 1080p30 on SDTV CCIR656, DPI-2, DBI-2 or DSI for
25 * Memory -> Overlay -> Channel -> FIFO -> 8 formatters -> DSI/DPI
26 * External 0..5 0..3 A,B, 6 x DSI bridge
29 * FIFOs A and B are for LCD and HDMI while FIFO CO/C1 are for
41 * helpers. We then provide a bridge to the DSI port, and on the DSI port
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/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx6-hdmi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx6-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 DWC HDMI TX Encoder
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
22 - fsl,imx6dl-hdmi
23 - fsl,imx6q-hdmi
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