Lines Matching +full:hdmi +full:- +full:bridge
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
13 #include <linux/hdmi.h>
21 #include <linux/dma-mapping.h>
24 #include <media/cec-notifier.h>
26 #include <linux/media-bus-format.h>
29 #include <drm/bridge/dw_hdmi.h>
40 #include "dw-hdmi-audio.h"
41 #include "dw-hdmi-cec.h"
42 #include "dw-hdmi.h"
49 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
127 int (*configure)(struct dw_hdmi *hdmi,
134 struct drm_bridge bridge;
170 enum drm_connector_force force; /* mutex-protected force state */
172 bool disabled; /* DRM has disabled our bridge */
173 bool bridge_is_on; /* indicates the bridge is on */
190 void (*enable_audio)(struct dw_hdmi *hdmi);
191 void (*disable_audio)(struct dw_hdmi *hdmi);
209 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
211 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
214 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
218 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
223 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
225 if (hdmi->plugged_cb && hdmi->codec_dev)
226 hdmi->plugged_cb(hdmi->codec_dev, plugged);
229 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
234 mutex_lock(&hdmi->mutex);
235 hdmi->plugged_cb = fn;
236 hdmi->codec_dev = codec_dev;
237 plugged = hdmi->last_connector_result == connector_status_connected;
238 handle_plugged_change(hdmi, plugged);
239 mutex_unlock(&hdmi->mutex);
245 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
247 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
250 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
253 hdmi_modb(hdmi, data << shift, mask, reg);
256 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
258 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
261 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
266 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
269 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
272 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
273 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
277 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
281 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
285 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
288 if (!hdmi->unwedge_state)
291 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
311 * its HDMI ports. It happened when the TV was powered on while the
325 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
327 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
332 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
334 struct dw_hdmi_i2c *i2c = hdmi->i2c;
337 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
340 if (!dw_hdmi_i2c_unwedge(hdmi))
341 return -EAGAIN;
344 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
346 return -EAGAIN;
350 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
351 return -EIO;
356 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
359 struct dw_hdmi_i2c *i2c = hdmi->i2c;
362 if (!i2c->is_regaddr) {
363 dev_dbg(hdmi->dev, "set read register address to 0\n");
364 i2c->slave_reg = 0x00;
365 i2c->is_regaddr = true;
368 while (length--) {
369 reinit_completion(&i2c->cmp);
371 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
372 if (i2c->is_segment)
373 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
376 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
379 ret = dw_hdmi_i2c_wait(hdmi);
383 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
385 i2c->is_segment = false;
390 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
393 struct dw_hdmi_i2c *i2c = hdmi->i2c;
396 if (!i2c->is_regaddr) {
398 i2c->slave_reg = buf[0];
399 length--;
401 i2c->is_regaddr = true;
404 while (length--) {
405 reinit_completion(&i2c->cmp);
407 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
408 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
409 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
412 ret = dw_hdmi_i2c_wait(hdmi);
423 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
424 struct dw_hdmi_i2c *i2c = hdmi->i2c;
430 * The internal I2C controller does not support the multi-byte
435 return -EOPNOTSUPP;
437 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
441 dev_dbg(hdmi->dev,
444 return -EOPNOTSUPP;
448 mutex_lock(&i2c->lock);
451 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
454 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
457 i2c->is_regaddr = false;
460 i2c->is_segment = false;
463 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
466 i2c->is_segment = true;
467 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
468 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
471 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
474 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
485 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
488 mutex_unlock(&i2c->lock);
503 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
509 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
511 return ERR_PTR(-ENOMEM);
513 mutex_init(&i2c->lock);
514 init_completion(&i2c->cmp);
516 adap = &i2c->adap;
517 adap->owner = THIS_MODULE;
518 adap->dev.parent = hdmi->dev;
519 adap->algo = &dw_hdmi_algorithm;
520 strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
521 i2c_set_adapdata(adap, hdmi);
525 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
526 devm_kfree(hdmi->dev, i2c);
530 hdmi->i2c = i2c;
532 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
537 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
541 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
544 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
548 hdmi_writeb(hdmi, ((cts >> 16) &
553 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
554 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
555 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
557 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
558 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
559 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
632 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
639 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
640 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
644 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
654 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
660 * can be up to 20 bits in total, so we need 64-bit math. Also
669 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
677 spin_lock_irq(&hdmi->audio_lock);
678 hdmi->audio_n = n;
679 hdmi->audio_cts = cts;
680 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
681 spin_unlock_irq(&hdmi->audio_lock);
684 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
686 mutex_lock(&hdmi->audio_mutex);
687 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
688 mutex_unlock(&hdmi->audio_mutex);
691 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
693 mutex_lock(&hdmi->audio_mutex);
694 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
695 hdmi->sample_rate);
696 mutex_unlock(&hdmi->audio_mutex);
699 void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width)
701 mutex_lock(&hdmi->audio_mutex);
702 hdmi->sample_width = width;
703 mutex_unlock(&hdmi->audio_mutex);
707 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm)
709 mutex_lock(&hdmi->audio_mutex);
710 hdmi->sample_non_pcm = non_pcm;
711 mutex_unlock(&hdmi->audio_mutex);
715 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
717 mutex_lock(&hdmi->audio_mutex);
718 hdmi->sample_rate = rate;
719 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
720 hdmi->sample_rate);
721 mutex_unlock(&hdmi->audio_mutex);
725 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
729 mutex_lock(&hdmi->audio_mutex);
730 hdmi->channels = cnt;
741 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
745 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
748 mutex_unlock(&hdmi->audio_mutex);
752 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
754 mutex_lock(&hdmi->audio_mutex);
756 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
758 mutex_unlock(&hdmi->audio_mutex);
762 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
765 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
767 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
768 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
771 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
773 if (!hdmi->curr_conn)
776 return hdmi->curr_conn->eld;
779 static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)
781 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
783 int ch_mask = BIT(hdmi->channels) - 1;
785 switch (hdmi->sample_rate) {
818 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
819 hdmi_enable_audio_clk(hdmi, true);
821 hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0);
822 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);
823 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3);
824 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4);
825 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5);
826 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6);
827 hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7);
828 hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8);
830 hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);
831 hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);
832 hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);
834 hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3);
837 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&
838 hdmi->sample_width == 32 && hdmi->sample_non_pcm)
839 hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2);
841 if (pdata->enable_audio)
842 pdata->enable_audio(hdmi,
843 hdmi->channels,
844 hdmi->sample_width,
845 hdmi->sample_rate,
846 hdmi->sample_non_pcm);
849 static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)
851 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
853 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
855 hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3);
856 if (pdata->disable_audio)
857 pdata->disable_audio(hdmi);
859 hdmi_enable_audio_clk(hdmi, false);
862 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
864 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
867 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
869 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
872 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
874 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
875 hdmi_enable_audio_clk(hdmi, true);
878 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
880 hdmi_enable_audio_clk(hdmi, false);
883 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
887 spin_lock_irqsave(&hdmi->audio_lock, flags);
888 hdmi->audio_enable = true;
889 if (hdmi->enable_audio)
890 hdmi->enable_audio(hdmi);
891 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
895 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
899 spin_lock_irqsave(&hdmi->audio_lock, flags);
900 hdmi->audio_enable = false;
901 if (hdmi->disable_audio)
902 hdmi->disable_audio(hdmi);
903 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
1000 static void hdmi_video_sample(struct dw_hdmi *hdmi)
1005 switch (hdmi->hdmi_data.enc_in_bus_format) {
1053 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
1059 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
1060 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
1061 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
1062 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
1063 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
1064 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
1065 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
1068 static int is_color_space_conversion(struct dw_hdmi *hdmi)
1070 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1073 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
1074 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
1077 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
1080 static int is_color_space_decimation(struct dw_hdmi *hdmi)
1082 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1085 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
1086 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
1092 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
1094 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
1097 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1098 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1104 static bool is_csc_needed(struct dw_hdmi *hdmi)
1106 return is_color_space_conversion(hdmi) ||
1107 is_color_space_decimation(hdmi) ||
1108 is_color_space_interpolation(hdmi);
1111 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1118 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1119 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1122 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1127 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1133 hdmi->hdmi_data.rgb_limited_range) {
1143 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1144 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1145 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1146 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1147 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1148 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1151 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1155 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1162 if (is_color_space_interpolation(hdmi))
1164 else if (is_color_space_decimation(hdmi))
1167 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1186 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1187 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1190 dw_hdmi_update_csc_coeffs(hdmi);
1194 * HDMI video packetizer is used to packetize the data.
1198 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1203 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1208 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1209 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1210 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1212 hdmi->hdmi_data.enc_out_bus_format)) {
1230 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1232 hdmi->hdmi_data.enc_out_bus_format)) {
1256 ((hdmi_data->pix_repet_factor <<
1259 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1262 * Source shall only send GCPs with non-zero CD to sinks
1265 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
1267 val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);
1272 hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);
1274 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1278 if (hdmi_data->pix_repet_factor > 1) {
1286 hdmi_modb(hdmi, vp_conf,
1290 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1293 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1311 hdmi_modb(hdmi, vp_conf,
1315 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1320 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1324 /* -----------------------------------------------------------------------------
1328 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1331 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1335 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1339 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1340 if (msec-- == 0)
1344 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1349 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1352 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1353 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1354 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1356 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1358 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1360 hdmi_phy_wait_i2c_done(hdmi, 1000);
1365 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
1369 if (hdmi->version < 0x200a)
1373 if (!hdmi->ddc)
1376 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1377 if (!display->hdmi.scdc.supported ||
1378 !display->hdmi.scdc.scrambling.supported)
1385 if (!display->hdmi.scdc.scrambling.low_rates &&
1386 display->max_tmds_clock <= 340000)
1394 * - The Source shall suspend transmission of the TMDS clock and data
1395 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1397 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1405 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
1408 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1410 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1411 if (dw_hdmi_support_scdc(hdmi, display)) {
1413 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1);
1415 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0);
1420 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1422 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1427 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1429 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1434 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1436 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1441 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1443 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1449 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1451 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1457 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1459 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1464 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1466 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1471 void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)
1474 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1475 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1479 void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
1482 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1483 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1487 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1489 hdmi_phy_test_clear(hdmi, 1);
1490 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1491 hdmi_phy_test_clear(hdmi, 0);
1495 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1497 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1501 if (phy->gen == 1) {
1502 dw_hdmi_phy_enable_tmds(hdmi, 0);
1503 dw_hdmi_phy_enable_powerdown(hdmi, true);
1507 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1514 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1522 dev_warn(hdmi->dev, "PHY failed to power down\n");
1524 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1526 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1529 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1531 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1535 if (phy->gen == 1) {
1536 dw_hdmi_phy_enable_powerdown(hdmi, false);
1539 dw_hdmi_phy_enable_tmds(hdmi, 0);
1540 dw_hdmi_phy_enable_tmds(hdmi, 1);
1544 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1545 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1549 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1557 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1558 return -ETIMEDOUT;
1561 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1566 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1570 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1574 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1575 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1576 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1580 /* PLL/MPLL Cfg - always match on final entry */
1581 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1582 if (mpixelclock <= mpll_config->mpixelclock)
1585 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1586 if (mpixelclock <= curr_ctrl->mpixelclock)
1589 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1590 if (mpixelclock <= phy_config->mpixelclock)
1593 if (mpll_config->mpixelclock == ~0UL ||
1594 curr_ctrl->mpixelclock == ~0UL ||
1595 phy_config->mpixelclock == ~0UL)
1596 return -EINVAL;
1598 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1600 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1602 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1605 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1606 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1609 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1610 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1612 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1616 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1622 static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1625 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1626 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1627 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1628 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1631 dw_hdmi_phy_power_off(hdmi);
1633 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1636 if (phy->has_svsret)
1637 dw_hdmi_phy_enable_svsret(hdmi, 1);
1639 dw_hdmi_phy_gen2_reset(hdmi);
1641 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1643 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1646 if (pdata->configure_phy)
1647 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1649 ret = phy->configure(hdmi, pdata, mpixelclock);
1651 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1660 return dw_hdmi_phy_power_on(hdmi);
1663 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1669 /* HDMI Phy spec says to do the phy initialization sequence twice */
1671 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1672 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1674 ret = hdmi_phy_configure(hdmi, display);
1682 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1684 dw_hdmi_phy_power_off(hdmi);
1687 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1690 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1695 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1698 u8 old_mask = hdmi->phy_mask;
1701 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1703 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1705 if (old_mask != hdmi->phy_mask)
1706 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1710 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1716 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1717 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1721 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1724 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1726 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1739 /* -----------------------------------------------------------------------------
1740 * HDMI TX Setup
1743 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1747 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1753 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1756 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1758 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1762 static void hdmi_config_AVI(struct dw_hdmi *hdmi,
1772 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1774 hdmi->hdmi_data.rgb_limited_range ?
1783 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1785 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1787 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1793 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1794 switch (hdmi->hdmi_data.enc_out_encoding) {
1796 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1804 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1841 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1847 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1855 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1859 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1861 /* AVI Data Byte 5- set up input and output pixel repetition */
1862 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1865 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1868 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1876 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1878 /* AVI Data Bytes 6-13 */
1879 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1880 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1881 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1882 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1883 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1884 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1885 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1886 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1889 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1910 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1914 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1917 /* Set the length of HDMI vendor specific InfoFrame payload */
1918 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1921 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1922 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1923 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1926 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1927 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1930 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1933 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1936 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1939 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1943 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
1946 const struct drm_connector_state *conn_state = connector->state;
1952 if (!hdmi->plat_data->use_drm_infoframe)
1955 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
1964 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1968 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
1969 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
1972 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
1974 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
1975 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
1979 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1984 const struct drm_hdmi_info *hdmi_info = &display->hdmi;
1985 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1989 vmode->mpixelclock = mode->clock * 1000;
1991 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1993 vmode->mtmdsclock = vmode->mpixelclock;
1995 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1997 hdmi->hdmi_data.enc_out_bus_format)) {
1999 vmode->mtmdsclock = vmode->mpixelclock * 2;
2002 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
2005 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
2010 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2011 vmode->mtmdsclock /= 2;
2013 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
2016 inv_val = (hdmi->hdmi_data.hdcp_enable ||
2017 (dw_hdmi_support_scdc(hdmi, display) &&
2018 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2019 hdmi_info->scdc.scrambling.low_rates)) ?
2023 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
2027 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
2031 inv_val |= (vmode->mdataenablepolarity ?
2035 if (hdmi->vic == 39)
2038 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
2042 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
2046 inv_val |= hdmi->sink_is_hdmi ?
2050 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
2052 hdisplay = mode->hdisplay;
2053 hblank = mode->htotal - mode->hdisplay;
2054 h_de_hs = mode->hsync_start - mode->hdisplay;
2055 hsync_len = mode->hsync_end - mode->hsync_start;
2061 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
2068 vdisplay = mode->vdisplay;
2069 vblank = mode->vtotal - mode->vdisplay;
2070 v_de_vs = mode->vsync_start - mode->vdisplay;
2071 vsync_len = mode->vsync_end - mode->vsync_start;
2077 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2085 if (dw_hdmi_support_scdc(hdmi, display)) {
2086 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2087 hdmi_info->scdc.scrambling.low_rates) {
2097 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
2099 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
2103 drm_scdc_set_scrambling(hdmi->curr_conn, 1);
2107 * that the quasi-static configuration bit
2112 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
2114 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
2116 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
2117 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
2119 drm_scdc_set_scrambling(hdmi->curr_conn, 0);
2124 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
2125 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
2128 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
2129 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
2132 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
2133 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
2136 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
2139 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
2140 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
2143 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
2146 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
2147 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
2150 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
2153 /* HDMI Initialization Step B.4 */
2154 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
2157 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
2158 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
2159 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
2162 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
2163 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
2164 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2167 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2172 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2173 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2175 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2176 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2179 if (is_csc_needed(hdmi)) {
2180 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2181 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2183 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2186 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2187 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2189 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2195 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2207 * The number of iterations matters and depends on the HDMI TX revision
2216 switch (hdmi->version) {
2226 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2228 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2230 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2233 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2235 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
2239 static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2245 hdmi_disable_overflow_interrupts(hdmi);
2247 hdmi->vic = drm_match_cea_mode(mode);
2249 if (!hdmi->vic) {
2250 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2252 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2255 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2256 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2257 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2258 (hdmi->vic == 17) || (hdmi->vic == 18))
2259 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2261 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2263 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2264 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2266 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
2267 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2270 if (hdmi->plat_data->input_bus_encoding)
2271 hdmi->hdmi_data.enc_in_encoding =
2272 hdmi->plat_data->input_bus_encoding;
2274 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2276 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
2277 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2279 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2283 hdmi->hdmi_data.pix_repet_factor = 0;
2284 hdmi->hdmi_data.hdcp_enable = 0;
2285 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2287 /* HDMI Initialization Step B.1 */
2288 hdmi_av_composer(hdmi, &connector->display_info, mode);
2290 /* HDMI Initializateion Step B.2 */
2291 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2292 &connector->display_info,
2293 &hdmi->previous_mode);
2296 hdmi->phy.enabled = true;
2298 /* HDMI Initialization Step B.3 */
2299 dw_hdmi_enable_video_path(hdmi);
2301 if (hdmi->sink_has_audio) {
2302 dev_dbg(hdmi->dev, "sink has audio support\n");
2304 /* HDMI Initialization Step E - Configure audio */
2305 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2306 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2310 if (hdmi->sink_is_hdmi) {
2311 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2313 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2314 hdmi_config_AVI(hdmi, connector, mode);
2315 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
2316 hdmi_config_drm_infoframe(hdmi, connector);
2318 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2321 hdmi_video_packetize(hdmi);
2322 hdmi_video_csc(hdmi);
2323 hdmi_video_sample(hdmi);
2324 hdmi_tx_hdcp_config(hdmi);
2326 dw_hdmi_clear_overflow(hdmi);
2331 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2340 * Disable top level interrupt bits in HDMI block
2342 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2346 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2349 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2350 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2351 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2352 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2353 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2354 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2355 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2356 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2357 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2358 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2359 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2360 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2361 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2362 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2365 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2366 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2367 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2368 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2369 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2370 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2371 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2372 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2373 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2374 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2376 /* Enable top level interrupt bits in HDMI block */
2379 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2382 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2384 hdmi->bridge_is_on = true;
2388 * is only be called when !hdmi->disabled.
2390 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2393 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2395 if (hdmi->phy.enabled) {
2396 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2397 hdmi->phy.enabled = false;
2400 hdmi->bridge_is_on = false;
2403 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2405 int force = hdmi->force;
2407 if (hdmi->disabled) {
2410 if (hdmi->rxsense)
2417 if (hdmi->bridge_is_on)
2418 dw_hdmi_poweroff(hdmi);
2420 if (!hdmi->bridge_is_on)
2421 dw_hdmi_poweron(hdmi);
2437 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2439 if (hdmi->phy.ops->update_hpd)
2440 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2441 hdmi->force, hdmi->disabled,
2442 hdmi->rxsense);
2445 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2449 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2450 hdmi->last_connector_result = result;
2455 static const struct drm_edid *dw_hdmi_edid_read(struct dw_hdmi *hdmi,
2461 if (!hdmi->ddc)
2464 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc);
2466 dev_dbg(hdmi->dev, "failed to get edid\n");
2471 * FIXME: This should use connector->display_info.is_hdmi and
2472 * connector->display_info.has_audio from a path that has read the EDID
2477 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2478 edid->width_cm, edid->height_cm);
2480 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2481 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2486 /* -----------------------------------------------------------------------------
2493 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2495 return dw_hdmi_detect(hdmi);
2500 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2505 drm_edid = dw_hdmi_edid_read(hdmi, connector);
2508 cec_notifier_set_phys_addr(hdmi->cec_notifier,
2509 connector->display_info.source_physical_address);
2523 struct drm_crtc *crtc = new_state->crtc;
2534 crtc_state->mode_changed = true;
2542 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2545 mutex_lock(&hdmi->mutex);
2546 hdmi->force = connector->force;
2547 dw_hdmi_update_power(hdmi);
2548 dw_hdmi_update_phy_mask(hdmi);
2549 mutex_unlock(&hdmi->mutex);
2567 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
2569 struct drm_connector *connector = &hdmi->connector;
2573 if (hdmi->version >= 0x200a)
2574 connector->ycbcr_420_allowed =
2575 hdmi->plat_data->ycbcr_420_allowed;
2577 connector->ycbcr_420_allowed = false;
2579 connector->interlace_allowed = 1;
2580 connector->polled = DRM_CONNECTOR_POLL_HPD;
2584 drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
2587 hdmi->ddc);
2597 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2600 drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
2604 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2606 return -ENOMEM;
2608 mutex_lock(&hdmi->cec_notifier_mutex);
2609 hdmi->cec_notifier = notifier;
2610 mutex_unlock(&hdmi->cec_notifier_mutex);
2615 /* -----------------------------------------------------------------------------
2616 * DRM Bridge Operations
2621 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2622 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2623 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2624 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2625 * - MEDIA_BUS_FMT_RGB888_1X24,
2626 * - MEDIA_BUS_FMT_YUV16_1X48,
2627 * - MEDIA_BUS_FMT_RGB161616_1X48,
2628 * - MEDIA_BUS_FMT_UYVY12_1X24,
2629 * - MEDIA_BUS_FMT_YUV12_1X36,
2630 * - MEDIA_BUS_FMT_RGB121212_1X36,
2631 * - MEDIA_BUS_FMT_UYVY10_1X20,
2632 * - MEDIA_BUS_FMT_YUV10_1X30,
2633 * - MEDIA_BUS_FMT_RGB101010_1X30,
2634 * - MEDIA_BUS_FMT_UYVY8_1X16,
2635 * - MEDIA_BUS_FMT_YUV8_1X24,
2641 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
2647 struct drm_connector *conn = conn_state->connector;
2648 struct drm_display_info *info = &conn->display_info;
2649 struct drm_display_mode *mode = &crtc_state->mode;
2650 u8 max_bpc = conn_state->max_requested_bpc;
2651 bool is_hdmi2_sink = info->hdmi.scdc.supported ||
2652 (info->color_formats & DRM_COLOR_FORMAT_YCBCR420);
2663 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
2664 if (list_is_singular(&bridge->encoder->bridge_chain) ||
2665 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
2676 if (conn->ycbcr_420_allowed &&
2681 if (max_bpc >= 16 && info->bpc == 16 &&
2682 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
2685 if (max_bpc >= 12 && info->bpc >= 12 &&
2686 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
2689 if (max_bpc >= 10 && info->bpc >= 10 &&
2690 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
2710 if (max_bpc >= 16 && info->bpc == 16) {
2711 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2717 if (max_bpc >= 12 && info->bpc >= 12) {
2718 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2721 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2727 if (max_bpc >= 10 && info->bpc >= 10) {
2728 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2731 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2737 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2740 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2750 * - MEDIA_BUS_FMT_RGB888_1X24
2751 * - MEDIA_BUS_FMT_YUV8_1X24
2752 * - MEDIA_BUS_FMT_UYVY8_1X16
2753 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2754 * - MEDIA_BUS_FMT_RGB101010_1X30
2755 * - MEDIA_BUS_FMT_YUV10_1X30
2756 * - MEDIA_BUS_FMT_UYVY10_1X20
2757 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2758 * - MEDIA_BUS_FMT_RGB121212_1X36
2759 * - MEDIA_BUS_FMT_YUV12_1X36
2760 * - MEDIA_BUS_FMT_UYVY12_1X24
2761 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2762 * - MEDIA_BUS_FMT_RGB161616_1X48
2763 * - MEDIA_BUS_FMT_YUV16_1X48
2764 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2770 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
2872 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
2877 struct dw_hdmi *hdmi = bridge->driver_private;
2879 hdmi->hdmi_data.enc_out_bus_format =
2880 bridge_state->output_bus_cfg.format;
2882 hdmi->hdmi_data.enc_in_bus_format =
2883 bridge_state->input_bus_cfg.format;
2885 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
2886 bridge_state->input_bus_cfg.format,
2887 bridge_state->output_bus_cfg.format);
2892 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
2896 struct dw_hdmi *hdmi = bridge->driver_private;
2899 return drm_bridge_attach(encoder, hdmi->next_bridge,
2900 bridge, flags);
2902 return dw_hdmi_connector_create(hdmi);
2905 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2907 struct dw_hdmi *hdmi = bridge->driver_private;
2909 mutex_lock(&hdmi->cec_notifier_mutex);
2910 cec_notifier_conn_unregister(hdmi->cec_notifier);
2911 hdmi->cec_notifier = NULL;
2912 mutex_unlock(&hdmi->cec_notifier_mutex);
2916 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2920 struct dw_hdmi *hdmi = bridge->driver_private;
2921 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2924 /* We don't support double-clocked modes */
2925 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2928 if (pdata->mode_valid)
2929 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
2935 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2939 struct dw_hdmi *hdmi = bridge->driver_private;
2941 mutex_lock(&hdmi->mutex);
2944 drm_mode_copy(&hdmi->previous_mode, mode);
2946 mutex_unlock(&hdmi->mutex);
2949 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
2952 struct dw_hdmi *hdmi = bridge->driver_private;
2954 mutex_lock(&hdmi->mutex);
2955 hdmi->disabled = true;
2956 hdmi->curr_conn = NULL;
2957 dw_hdmi_update_power(hdmi);
2958 dw_hdmi_update_phy_mask(hdmi);
2959 handle_plugged_change(hdmi, false);
2960 mutex_unlock(&hdmi->mutex);
2963 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
2966 struct dw_hdmi *hdmi = bridge->driver_private;
2970 bridge->encoder);
2972 mutex_lock(&hdmi->mutex);
2973 hdmi->disabled = false;
2974 hdmi->curr_conn = connector;
2975 dw_hdmi_update_power(hdmi);
2976 dw_hdmi_update_phy_mask(hdmi);
2977 handle_plugged_change(hdmi, true);
2978 mutex_unlock(&hdmi->mutex);
2982 dw_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
2984 struct dw_hdmi *hdmi = bridge->driver_private;
2986 return dw_hdmi_detect(hdmi);
2989 static const struct drm_edid *dw_hdmi_bridge_edid_read(struct drm_bridge *bridge,
2992 struct dw_hdmi *hdmi = bridge->driver_private;
2994 return dw_hdmi_edid_read(hdmi, connector);
3014 /* -----------------------------------------------------------------------------
3018 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
3020 struct dw_hdmi_i2c *i2c = hdmi->i2c;
3023 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
3027 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
3029 i2c->stat = stat;
3031 complete(&i2c->cmp);
3038 struct dw_hdmi *hdmi = dev_id;
3042 if (hdmi->i2c)
3043 ret = dw_hdmi_i2c_irq(hdmi);
3045 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3047 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3054 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
3056 mutex_lock(&hdmi->mutex);
3058 if (!hdmi->force) {
3064 hdmi->rxsense = false;
3073 hdmi->rxsense = true;
3075 dw_hdmi_update_power(hdmi);
3076 dw_hdmi_update_phy_mask(hdmi);
3078 mutex_unlock(&hdmi->mutex);
3084 struct dw_hdmi *hdmi = dev_id;
3088 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3089 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
3090 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
3105 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
3109 * load - in other words, there's something listening on the
3112 * ask the source to re-read the EDID.
3116 dw_hdmi_setup_rx_sense(hdmi,
3121 mutex_lock(&hdmi->cec_notifier_mutex);
3122 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
3123 mutex_unlock(&hdmi->cec_notifier_mutex);
3134 dev_dbg(hdmi->dev, "EVENT=%s\n",
3138 if (hdmi->bridge.dev) {
3139 drm_helper_hpd_irq_event(hdmi->bridge.dev);
3140 drm_bridge_hpd_notify(&hdmi->bridge, status);
3144 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
3145 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
3154 .name = "DWC HDMI TX PHY",
3170 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
3175 .name = "DWC HDMI 3D TX PHY",
3180 .name = "DWC HDMI 2.0 TX PHY",
3190 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
3195 phy_type = hdmi->plat_data->phy_force_vendor ?
3197 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
3201 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3202 dev_err(hdmi->dev,
3203 "Vendor HDMI PHY not supported by glue layer\n");
3204 return -ENODEV;
3207 hdmi->phy.ops = hdmi->plat_data->phy_ops;
3208 hdmi->phy.data = hdmi->plat_data->phy_data;
3209 hdmi->phy.name = hdmi->plat_data->phy_name;
3216 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3217 hdmi->phy.name = dw_hdmi_phys[i].name;
3218 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3221 !hdmi->plat_data->configure_phy) {
3222 dev_err(hdmi->dev, "%s requires platform support\n",
3223 hdmi->phy.name);
3224 return -ENODEV;
3231 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3232 return -ENODEV;
3235 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
3237 mutex_lock(&hdmi->mutex);
3238 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
3239 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3240 mutex_unlock(&hdmi->mutex);
3243 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
3245 mutex_lock(&hdmi->mutex);
3246 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
3247 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3248 mutex_unlock(&hdmi->mutex);
3272 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
3274 initialize_hdmi_ih_mutes(hdmi);
3277 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
3281 dw_hdmi_i2c_init(hdmi);
3283 if (hdmi->phy.ops->setup_hpd)
3284 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
3287 /* -----------------------------------------------------------------------------
3288 * Probe/remove API, used from platforms based on the DRM bridge API.
3291 static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi)
3295 if (!hdmi->plat_data->output_port)
3299 remote = of_graph_get_remote_node(hdmi->dev->of_node,
3300 hdmi->plat_data->output_port,
3301 -1);
3303 return -ENODEV;
3305 hdmi->next_bridge = of_drm_find_bridge(remote);
3307 if (!hdmi->next_bridge)
3308 return -EPROBE_DEFER;
3313 bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi)
3315 return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format);
3322 struct device *dev = &pdev->dev;
3323 struct device_node *np = dev->of_node;
3327 struct dw_hdmi *hdmi;
3338 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi, bridge, &dw_hdmi_bridge_funcs);
3339 if (IS_ERR(hdmi))
3340 return hdmi;
3342 hdmi->plat_data = plat_data;
3343 hdmi->dev = dev;
3344 hdmi->sample_rate = 48000;
3345 hdmi->channels = 2;
3346 hdmi->disabled = true;
3347 hdmi->rxsense = true;
3348 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
3349 hdmi->mc_clkdis = 0x7f;
3350 hdmi->last_connector_result = connector_status_disconnected;
3352 mutex_init(&hdmi->mutex);
3353 mutex_init(&hdmi->audio_mutex);
3354 mutex_init(&hdmi->cec_notifier_mutex);
3355 spin_lock_init(&hdmi->audio_lock);
3357 ret = dw_hdmi_parse_dt(hdmi);
3361 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
3363 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
3365 if (!hdmi->ddc) {
3366 dev_dbg(hdmi->dev, "failed to read ddc node\n");
3367 return ERR_PTR(-EPROBE_DEFER);
3371 dev_dbg(hdmi->dev, "no ddc property found\n");
3374 if (!plat_data->regm) {
3377 of_property_read_u32(np, "reg-io-width", &val);
3381 hdmi->reg_shift = 2;
3387 dev_err(dev, "reg-io-width must be 1 or 4\n");
3388 return ERR_PTR(-EINVAL);
3392 hdmi->regs = devm_ioremap_resource(dev, iores);
3393 if (IS_ERR(hdmi->regs)) {
3394 ret = PTR_ERR(hdmi->regs);
3398 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
3399 if (IS_ERR(hdmi->regm)) {
3401 ret = PTR_ERR(hdmi->regm);
3405 hdmi->regm = plat_data->regm;
3408 clk = devm_clk_get_enabled(hdmi->dev, "isfr");
3411 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3415 clk = devm_clk_get_enabled(hdmi->dev, "iahb");
3418 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3422 clk = devm_clk_get_optional_enabled(hdmi->dev, "cec");
3425 if (ret != -EPROBE_DEFER)
3426 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3432 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
3433 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
3434 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
3435 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
3439 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3440 hdmi->version, prod_id0, prod_id1);
3441 ret = -ENODEV;
3445 ret = dw_hdmi_detect_phy(hdmi);
3449 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3450 hdmi->version >> 12, hdmi->version & 0xfff,
3452 hdmi->phy.name);
3454 dw_hdmi_init_hw(hdmi);
3464 dev_name(dev), hdmi);
3472 hdmi_init_clk_regenerator(hdmi);
3474 /* If DDC bus is not specified, try to register HDMI I2C bus */
3475 if (!hdmi->ddc) {
3477 hdmi->pinctrl = devm_pinctrl_get(dev);
3478 if (!IS_ERR(hdmi->pinctrl)) {
3479 hdmi->unwedge_state =
3480 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
3481 hdmi->default_state =
3482 pinctrl_lookup_state(hdmi->pinctrl, "default");
3484 if (IS_ERR(hdmi->default_state) ||
3485 IS_ERR(hdmi->unwedge_state)) {
3486 if (!IS_ERR(hdmi->unwedge_state))
3489 hdmi->default_state = NULL;
3490 hdmi->unwedge_state = NULL;
3494 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
3495 if (IS_ERR(hdmi->ddc))
3496 hdmi->ddc = NULL;
3499 hdmi->bridge.driver_private = hdmi;
3500 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
3502 hdmi->bridge.interlace_allowed = true;
3503 hdmi->bridge.ddc = hdmi->ddc;
3504 hdmi->bridge.of_node = pdev->dev.of_node;
3505 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
3507 if (hdmi->version >= 0x200a)
3508 hdmi->bridge.ycbcr_420_allowed = plat_data->ycbcr_420_allowed;
3514 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
3515 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
3520 audio.phys = iores->start;
3521 audio.base = hdmi->regs;
3523 audio.hdmi = hdmi;
3525 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
3526 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
3528 pdevinfo.name = "dw-hdmi-ahb-audio";
3532 hdmi->audio = platform_device_register_full(&pdevinfo);
3536 audio.hdmi = hdmi;
3540 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
3541 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
3543 pdevinfo.name = "dw-hdmi-i2s-audio";
3547 hdmi->audio = platform_device_register_full(&pdevinfo);
3551 audio.phys = iores->start;
3552 audio.base = hdmi->regs;
3554 audio.hdmi = hdmi;
3557 hdmi->enable_audio = dw_hdmi_gp_audio_enable;
3558 hdmi->disable_audio = dw_hdmi_gp_audio_disable;
3560 pdevinfo.name = "dw-hdmi-gp-audio";
3565 hdmi->audio = platform_device_register_full(&pdevinfo);
3568 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
3569 cec.hdmi = hdmi;
3573 pdevinfo.name = "dw-hdmi-cec";
3578 hdmi->cec = platform_device_register_full(&pdevinfo);
3581 drm_bridge_add(&hdmi->bridge);
3583 return hdmi;
3586 i2c_put_adapter(hdmi->ddc);
3592 void dw_hdmi_remove(struct dw_hdmi *hdmi)
3594 drm_bridge_remove(&hdmi->bridge);
3596 if (hdmi->audio && !IS_ERR(hdmi->audio))
3597 platform_device_unregister(hdmi->audio);
3598 if (!IS_ERR(hdmi->cec))
3599 platform_device_unregister(hdmi->cec);
3602 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3604 if (hdmi->i2c)
3605 i2c_del_adapter(&hdmi->i2c->adap);
3607 i2c_put_adapter(hdmi->ddc);
3611 /* -----------------------------------------------------------------------------
3618 struct dw_hdmi *hdmi;
3621 hdmi = dw_hdmi_probe(pdev, plat_data);
3622 if (IS_ERR(hdmi))
3623 return hdmi;
3625 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
3627 dw_hdmi_remove(hdmi);
3631 return hdmi;
3635 void dw_hdmi_unbind(struct dw_hdmi *hdmi)
3637 dw_hdmi_remove(hdmi);
3641 void dw_hdmi_resume(struct dw_hdmi *hdmi)
3643 dw_hdmi_init_hw(hdmi);
3648 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3649 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3651 MODULE_DESCRIPTION("DW HDMI transmitter driver");
3653 MODULE_ALIAS("platform:dw-hdmi");