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/linux/drivers/gpu/drm/arm/
H A Dhdlcd_drv.c9 * ARM HDLCD Driver
44 struct hdlcd_drm_private *hdlcd = arg; in hdlcd_irq() local
47 irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS); in hdlcd_irq()
51 atomic_inc(&hdlcd->buffer_underrun_count); in hdlcd_irq()
54 atomic_inc(&hdlcd->dma_end_count); in hdlcd_irq()
57 atomic_inc(&hdlcd->bus_error_count); in hdlcd_irq()
60 atomic_inc(&hdlcd->vsync_count); in hdlcd_irq()
64 drm_crtc_handle_vblank(&hdlcd->crtc); in hdlcd_irq()
67 hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status); in hdlcd_irq()
72 static int hdlcd_irq_install(struct hdlcd_drm_private *hdlcd) in hdlcd_irq_install() argument
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H A Dhdlcd_crtc.c9 * Implementation of a CRTC class for the HDLCD driver.
32 * The HDLCD controller is a dumb RGB streamer that gets connected to
40 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); in hdlcd_crtc_cleanup() local
43 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0); in hdlcd_crtc_cleanup()
49 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); in hdlcd_crtc_enable_vblank() local
50 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); in hdlcd_crtc_enable_vblank()
52 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC); in hdlcd_crtc_enable_vblank()
59 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); in hdlcd_crtc_disable_vblank() local
60 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK); in hdlcd_crtc_disable_vblank()
62 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC); in hdlcd_crtc_disable_vblank()
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H A Dhdlcd_drv.h3 * ARM HDLCD Controller register definition
27 static inline void hdlcd_write(struct hdlcd_drm_private *hdlcd, in hdlcd_write() argument
30 writel(value, hdlcd->mmio + reg); in hdlcd_write()
33 static inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg) in hdlcd_read() argument
35 return readl(hdlcd->mmio + reg); in hdlcd_read()
39 void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd);
H A DMakefile2 hdlcd-y := hdlcd_drv.o hdlcd_crtc.o
3 obj-$(CONFIG_DRM_HDLCD) += hdlcd.o
H A Dhdlcd_regs.h8 * ARM HDLCD Controller register definition
/linux/Documentation/devicetree/bindings/display/
H A Darm,hdlcd.yaml4 $id: http://devicetree.org/schemas/display/arm,hdlcd.yaml#
7 title: Arm HDLCD display controller
14 The Arm HDLCD is a display controller found on several development platforms
15 produced by ARM Ltd and in more modern of its Fast Models. The HDLCD is an
21 const: arm,hdlcd
62 hdlcd@2b000000 {
63 compatible = "arm,hdlcd";
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2p-ca5s.dts72 hdlcd@2a110000 {
73 compatible = "arm,hdlcd";
176 /* HDLCD */
H A Dvexpress-v2p-ca15-tc1.dts70 hdlcd@2b000000 {
71 compatible = "arm,hdlcd";
164 /* HDLCD PLL reference clock */
H A Dvexpress-v2p-ca15_a7.dts134 hdlcd@2b000000 {
135 compatible = "arm,hdlcd";
302 /* HDLCD PLL reference clock */
/linux/drivers/gpu/drm/pl111/
H A Dpl111_versatile.c397 * Check if we have a CLCD or HDLCD on the core tile by checking if a in pl111_vexpress_clcd_init()
398 * CLCD or HDLCD is available in the root of the device tree. in pl111_vexpress_clcd_init()
411 if (of_device_is_compatible(child, "arm,hdlcd")) { in pl111_vexpress_clcd_init()
421 * If there is a coretile HDLCD and it has a driver, in pl111_vexpress_clcd_init()
/linux/arch/arm64/boot/dts/arm/
H A Djuno-scmi.dtsi34 hdlcd@7ff50000 {
38 hdlcd@7ff60000 {
H A Djuno-base.dtsi868 hdlcd@7ff50000 {
869 compatible = "arm,hdlcd";
883 hdlcd@7ff60000 {
884 compatible = "arm,hdlcd";
/linux/
H A DMAINTAINERS1831 ARM HDLCD DRM DRIVER
1834 F: Documentation/devicetree/bindings/display/arm,hdlcd.yaml