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/linux/drivers/clk/
H A Dclk-stm32h7.c73 "hclk", "pll1_q", "pll2_r", "per_ck" };
76 "hclk", "pll1_q", "pll2_r", "per_ck" };
517 hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre", in register_core_and_bus_clocks()
527 hws[PCLK3] = clk_hw_register_divider_table(NULL, "pclk3", "hclk", 0, in register_core_and_bus_clocks()
533 hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0, in register_core_and_bus_clocks()
542 hws[PCLK2] = clk_hw_register_divider_table(NULL, "pclk2", "hclk", 0, in register_core_and_bus_clocks()
551 hws[PCLK4] = clk_hw_register_divider_table(NULL, "pclk4", "hclk", 0, in register_core_and_bus_clocks()
998 PER_CLK(RCC_AHB3ENR, 31, "d1sram1", "hclk"),
999 PER_CLK(RCC_AHB3ENR, 30, "itcm", "hclk"),
1000 PER_CLK(RCC_AHB3ENR, 29, "dtcm2", "hclk"),
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx1.c22 static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
52 clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4); in mx1_clocks_init_dt()
58 clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); in mx1_clocks_init_dt()
59 clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); in mx1_clocks_init_dt()
60 clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); in mx1_clocks_init_dt()
61 clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); in mx1_clocks_init_dt()
62 clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); in mx1_clocks_init_dt()
63 clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); in mx1_clocks_init_dt()
/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml204 - description: HCLK which used for host
210 - const: hclk
224 - description: HCLK which used for host
231 - const: hclk
265 - description: HCLK which used for host
273 - const: hclk
289 - description: HCLK which used for host
295 - const: hclk
312 - description: HCLK which used for host
318 - const: hclk
[all …]
/linux/drivers/net/ethernet/cadence/
H A Dmacb_pci.c68 plat_data.hclk = clk_register_fixed_rate(&pdev->dev, "hclk", NULL, 0, in macb_probe()
70 if (IS_ERR(plat_data.hclk)) { in macb_probe()
71 err = PTR_ERR(plat_data.hclk); in macb_probe()
99 clk_unregister(plat_data.hclk); in macb_probe()
114 clk_unregister(plat_data->hclk); in macb_remove()
/linux/drivers/char/hw_random/
H A Djh7110-trng.c98 struct clk *hclk; member
241 clk_disable_unprepare(trng->hclk); in starfive_trng_cleanup()
306 trng->hclk = devm_clk_get(&pdev->dev, "hclk"); in starfive_trng_probe()
307 if (IS_ERR(trng->hclk)) in starfive_trng_probe()
308 return dev_err_probe(&pdev->dev, PTR_ERR(trng->hclk), in starfive_trng_probe()
321 clk_prepare_enable(trng->hclk); in starfive_trng_probe()
344 clk_disable_unprepare(trng->hclk); in starfive_trng_probe()
356 clk_disable_unprepare(trng->hclk); in starfive_trng_suspend()
366 clk_prepare_enable(trng->hclk); in starfive_trng_resume()
/linux/Documentation/devicetree/bindings/usb/
H A Datmel-usb.txt13 "hclk" for the host clock
25 clock-names = "ohci_clk", "hclk", "uhpck";
67 "hclk" for the AHB clock
78 clock-names = "pclk", "hclk";
98 "hclk" for the host clock
123 clock-names = "hclk", "pclk";
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
227 hclk: hclk@0 { label
229 compatible = "st,nomadik-hclk-clock";
232 /* The PCLK domain uses HCLK right off */
238 clocks = <&hclk>;
302 clocks = <&hclk>;
308 clocks = <&hclk>;
314 clocks = <&hclk>;
320 clocks = <&hclk>;
326 clocks = <&hclk>;
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dcommon.c47 int hclk; in get_hclk() local
50 * HCLK tick rate is configured by DEV_D[7:5] pins. in get_hclk()
54 hclk = 166666667; in get_hclk()
57 hclk = 200000000; in get_hclk()
60 hclk = 266666667; in get_hclk()
63 hclk = 333333333; in get_hclk()
66 hclk = 400000000; in get_hclk()
69 panic("unknown HCLK PLL setting: %.8x\n", in get_hclk()
73 return hclk; in get_hclk()
76 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) in get_pclk_l2clk() argument
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dst,nomadik.txt34 HCLK nodes: these represent the clock gates on individual
35 lines from the HCLK clock tree and the gate for individual
38 Requires properties for the HCLK nodes:
39 - compatible: must be "st,nomadik-hclk-clock"
/linux/Documentation/devicetree/bindings/mtd/
H A Dfsmc-nand.txt19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
H A Drenesas-nandc.yaml36 - const: hclk
62 clock-names = "hclk", "eclk";
/linux/arch/arm/mach-lpc32xx/
H A Dpm.c21 * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
22 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
26 * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
57 * HCLK PLL state is restored
H A Dsuspend.S89 @ Save HCLK PLL state and disable HCLK PLL
105 @ Restore original HCLK PLL value and wait for PLL lock
/linux/drivers/spi/
H A Dspi-rockchip-sfc.c177 struct clk *hclk; member
646 sfc->hclk = devm_clk_get(&pdev->dev, "hclk_sfc"); in rockchip_sfc_probe()
647 if (IS_ERR(sfc->hclk)) in rockchip_sfc_probe()
648 return dev_err_probe(&pdev->dev, PTR_ERR(sfc->hclk), in rockchip_sfc_probe()
662 ret = clk_prepare_enable(sfc->hclk); in rockchip_sfc_probe()
730 clk_disable_unprepare(sfc->hclk); in rockchip_sfc_probe()
744 clk_disable_unprepare(sfc->hclk); in rockchip_sfc_remove()
753 clk_disable_unprepare(sfc->hclk); in rockchip_sfc_runtime_suspend()
763 ret = clk_prepare_enable(sfc->hclk); in rockchip_sfc_runtime_resume()
769 clk_disable_unprepare(sfc->hclk); in rockchip_sfc_runtime_resume()
H A Dspi-sun4i.c80 struct clk *hclk; member
397 ret = clk_prepare_enable(sspi->hclk); in sun4i_spi_runtime_resume()
415 clk_disable_unprepare(sspi->hclk); in sun4i_spi_runtime_resume()
426 clk_disable_unprepare(sspi->hclk); in sun4i_spi_runtime_suspend()
478 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); in sun4i_spi_probe()
479 if (IS_ERR(sspi->hclk)) { in sun4i_spi_probe()
481 ret = PTR_ERR(sspi->hclk); in sun4i_spi_probe()
/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml85 - enum: [ ether_clk, hclk, pclk ]
86 - enum: [ hclk, pclk ]
188 clock-names = "pclk", "hclk", "tx_clk";
215 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
/linux/Documentation/devicetree/bindings/sound/
H A Drockchip,rk3576-sai.yaml47 - const: hclk
53 - description: reset for the hclk domain
127 clock-names = "mclk", "hclk";
/linux/Documentation/devicetree/bindings/media/
H A Drockchip-isp1.yaml42 - description: ISP AHB clock (for imx8mp, hclk)
52 - const: hclk
191 clock-names = "isp", "aclk", "hclk";
279 clock-names = "isp", "aclk", "hclk", "pclk";
/linux/drivers/slimbus/
H A Dqcom-ctrl.c117 struct clk *hclk; member
282 clk_prepare_enable(ctrl->hclk); in qcom_clk_pause_wakeup()
498 ctrl->hclk = devm_clk_get(&pdev->dev, "iface"); in qcom_slim_probe()
499 if (IS_ERR(ctrl->hclk)) in qcom_slim_probe()
500 return PTR_ERR(ctrl->hclk); in qcom_slim_probe()
562 ret = clk_prepare_enable(ctrl->hclk); in qcom_slim_probe()
623 clk_disable_unprepare(ctrl->hclk); in qcom_slim_probe()
637 clk_disable_unprepare(ctrl->hclk); in qcom_slim_remove()
657 clk_disable_unprepare(ctrl->hclk); in qcom_slim_runtime_suspend()
/linux/Documentation/devicetree/bindings/rng/
H A Dstarfive,jh7110-trng.yaml30 - const: hclk
55 clock-names = "hclk", "ahb";
/linux/Documentation/devicetree/bindings/net/can/
H A Dbosch,m_can.yaml50 - const: hclk
147 clock-names = "hclk", "cclk";
164 clock-names = "hclk", "cclk";
/linux/sound/soc/rockchip/
H A Drockchip_sai.c45 struct clk *hclk; member
247 clk_disable_unprepare(sai->hclk); in rockchip_sai_runtime_suspend()
257 ret = clk_prepare_enable(sai->hclk); in rockchip_sai_runtime_resume()
276 clk_disable_unprepare(sai->hclk); in rockchip_sai_runtime_resume()
324 * It is advised to reset the hclk domain before resetting the mclk in rockchip_sai_reset()
1454 sai->hclk = devm_clk_get(&pdev->dev, "hclk"); in rockchip_sai_probe()
1455 if (IS_ERR(sai->hclk)) { in rockchip_sai_probe()
1456 return dev_err_probe(&pdev->dev, PTR_ERR(sai->hclk), in rockchip_sai_probe()
1457 "Failed to get hclk\n"); in rockchip_sai_probe()
1460 ret = clk_prepare_enable(sai->hclk); in rockchip_sai_probe()
[all …]
H A Drockchip_i2s_tdm.c50 struct clk *hclk; member
132 clk_disable_unprepare(i2s_tdm->hclk); in i2s_tdm_runtime_suspend()
142 ret = clk_prepare_enable(i2s_tdm->hclk); in i2s_tdm_runtime_resume()
162 clk_disable_unprepare(i2s_tdm->hclk); in i2s_tdm_runtime_resume()
1272 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk"); in rockchip_i2s_tdm_probe()
1273 if (IS_ERR(i2s_tdm->hclk)) { in rockchip_i2s_tdm_probe()
1274 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk), in rockchip_i2s_tdm_probe()
1275 "Failed to get clock hclk\n"); in rockchip_i2s_tdm_probe()
1332 ret = clk_prepare_enable(i2s_tdm->hclk); in rockchip_i2s_tdm_probe()
1335 "Failed to enable clock hclk\n"); in rockchip_i2s_tdm_probe()
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Drenesas,rzn1-rtc.yaml42 - const: hclk
71 clock-names = "hclk";
/linux/Documentation/devicetree/bindings/crypto/
H A Dstarfive,jh7110-crypto.yaml29 - const: hclk
89 clock-names = "hclk", "ahb";

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