Searched +full:hb +full:- +full:ddr +full:- +full:ctrl (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Calxeda DDR memory controller10 The Calxeda DDR memory controller is initialised and programmed by the15 - Andre Przywara <andre.przywara@arm.com>20 - calxeda,hb-ddr-ctrl21 - calxeda,ecx-2000-ddr-ctrl30 - compatible[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright 2011-2012 Calxeda, Inc.6 /dts-v1/;14 #address-cells = <1>;15 #size-cells = <1>;18 #address-cells = <1>;19 #size-cells = <0>;22 compatible = "arm,cortex-a9";25 next-level-cache = <&L2>;27 clock-names = "cpu";[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright 2011-2012 Calxeda, Inc.17 /* DDR Ctrlr Error Registers */36 /* DDR Ctrlr Interrupt Registers */57 struct hb_mc_drvdata *drvdata = mci->pvt_info; in highbank_mc_err_handler()61 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS); in highbank_mc_err_handler()64 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR); in highbank_mc_err_handler()68 0, 0, -1, in highbank_mc_err_handler()69 mci->ctl_name, ""); in highbank_mc_err_handler()72 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT); in highbank_mc_err_handler()[all …]