Lines Matching +full:hb +full:- +full:ddr +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
17 /* DDR Ctrlr Error Registers */
36 /* DDR Ctrlr Interrupt Registers */
57 struct hb_mc_drvdata *drvdata = mci->pvt_info; in highbank_mc_err_handler()
61 status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS); in highbank_mc_err_handler()
64 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR); in highbank_mc_err_handler()
68 0, 0, -1, in highbank_mc_err_handler()
69 mci->ctl_name, ""); in highbank_mc_err_handler()
72 u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT); in highbank_mc_err_handler()
74 err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR); in highbank_mc_err_handler()
78 0, 0, -1, in highbank_mc_err_handler()
79 mci->ctl_name, ""); in highbank_mc_err_handler()
83 writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK); in highbank_mc_err_handler()
89 struct hb_mc_drvdata *pdata = mci->pvt_info; in highbank_mc_err_inject()
92 reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT); in highbank_mc_err_inject()
95 writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT); in highbank_mc_err_inject()
107 return -EINVAL; in highbank_mc_inject_ctrl()
139 { .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
140 { .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
159 id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev); in highbank_mc_probe()
161 return -ENODEV; in highbank_mc_probe()
172 return -ENOMEM; in highbank_mc_probe()
174 mci->pdev = &pdev->dev; in highbank_mc_probe()
175 drvdata = mci->pvt_info; in highbank_mc_probe()
178 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { in highbank_mc_probe()
179 res = -ENOMEM; in highbank_mc_probe()
185 dev_err(&pdev->dev, "Unable to get mem resource\n"); in highbank_mc_probe()
186 res = -ENODEV; in highbank_mc_probe()
190 if (!devm_request_mem_region(&pdev->dev, r->start, in highbank_mc_probe()
191 resource_size(r), dev_name(&pdev->dev))) { in highbank_mc_probe()
192 dev_err(&pdev->dev, "Error while requesting mem region\n"); in highbank_mc_probe()
193 res = -EBUSY; in highbank_mc_probe()
197 base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); in highbank_mc_probe()
199 dev_err(&pdev->dev, "Unable to map regs\n"); in highbank_mc_probe()
200 res = -ENOMEM; in highbank_mc_probe()
204 settings = id->data; in highbank_mc_probe()
205 drvdata->mc_err_base = base + settings->err_offset; in highbank_mc_probe()
206 drvdata->mc_int_base = base + settings->int_offset; in highbank_mc_probe()
208 control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3; in highbank_mc_probe()
210 dev_err(&pdev->dev, "No ECC present, or ECC disabled\n"); in highbank_mc_probe()
211 res = -ENODEV; in highbank_mc_probe()
215 mci->mtype_cap = MEM_FLAG_DDR3; in highbank_mc_probe()
216 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in highbank_mc_probe()
217 mci->edac_cap = EDAC_FLAG_SECDED; in highbank_mc_probe()
218 mci->mod_name = pdev->dev.driver->name; in highbank_mc_probe()
219 mci->ctl_name = id->compatible; in highbank_mc_probe()
220 mci->dev_name = dev_name(&pdev->dev); in highbank_mc_probe()
221 mci->scrub_mode = SCRUB_SW_SRC; in highbank_mc_probe()
224 dimm = *mci->dimms; in highbank_mc_probe()
225 dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1; in highbank_mc_probe()
226 dimm->grain = 8; in highbank_mc_probe()
227 dimm->dtype = DEV_X8; in highbank_mc_probe()
228 dimm->mtype = MEM_DDR3; in highbank_mc_probe()
229 dimm->edac_mode = EDAC_SECDED; in highbank_mc_probe()
236 res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler, in highbank_mc_probe()
237 0, dev_name(&pdev->dev), mci); in highbank_mc_probe()
239 dev_err(&pdev->dev, "Unable to request irq %d\n", irq); in highbank_mc_probe()
243 devres_close_group(&pdev->dev, NULL); in highbank_mc_probe()
246 edac_mc_del_mc(&pdev->dev); in highbank_mc_probe()
248 devres_release_group(&pdev->dev, NULL); in highbank_mc_probe()
258 edac_mc_del_mc(&pdev->dev); in highbank_mc_remove()