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Searched +full:hash +full:- +full:accelerator (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
39 called padlock-aes.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
76 or Accelerator (CEXxA) mode.
87 - A pkey base and API kernel module (pkey.ko) which offers the
89 and the sysfs API and the in-kernel API to the crypto cipher
91 - A pkey pckmo kernel module (pkey-pckmo.ko) which is automatically
94 - A pkey CCA kernel module (pkey-cca.ko) which is automatically
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H A Dimg-hash.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Interface structure taken from omap-sham driver
10 #include <linux/dma-mapping.h>
20 #include <crypto/internal/hash.h>
151 return readl_relaxed(hdev->io_base + offset); in img_hash_read()
157 writel_relaxed(value, hdev->io_base + offset); in img_hash_write()
167 struct img_hash_request_ctx *ctx = ahash_request_ctx(hdev->req); in img_hash_start()
170 if (ctx->flags & DRIVER_FLAGS_MD5) in img_hash_start()
172 else if (ctx->flags & DRIVER_FLAGS_SHA1) in img_hash_start()
174 else if (ctx->flags & DRIVER_FLAGS_SHA224) in img_hash_start()
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/linux/drivers/crypto/stm32/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Support for STM32 hash accelerators"
14 This enables support for the HASH hw accelerator which can be found
24 This enables support for the CRYP (AES/DES/TDES) hw accelerator which
/linux/drivers/crypto/allwinner/
H A DKconfig9 tristate "Support for Allwinner Security System cryptographic accelerator"
19 Some Allwinner SoC have a crypto accelerator named
22 and SHA1 and MD5 hash algorithms.
25 will be called sun4i-ss.
32 Select this option if you want to provide kernel-side support for
33 the Pseudo-Random Number Generator found in the Security System.
36 bool "Enable sun4i-ss stats"
40 Say y to enable sun4i-ss debug stats.
41 This will create /sys/kernel/debug/sun4i-ss/stats for displaying
60 will be called sun8i-ce.
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/linux/Documentation/devicetree/bindings/crypto/
H A Daspeed,ast2500-hace.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/aspeed,ast2500-hace.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
10 - Neal Liu <neal_liu@aspeedtech.com>
13 The Hash and Crypto Engine (HACE) is designed to accelerate the throughput
14 of hash data digest, encryption, and decryption. Basically, HACE can be
15 divided into two independently engines - Hash Engine and Crypto Engine.
20 - aspeed,ast2500-hace
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/linux/drivers/crypto/caam/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
12 tristate "Freescale CAAM-Multicore platform driver backend"
18 Enables the driver module for Freescale's Cryptographic Accelerator
41 Freescale's Cryptographic Accelerator
56 range 2-9 (ring size 4-512).
82 raising an interrupt, in the range 1-255. Note that a selection
94 threshold. Range is 1-65535.
128 bool "Register hash algorithm implementations with Crypto API"
169 Selecting this will enable a self-test to run for the
194 (MC) fsl-mc bus.
/linux/drivers/crypto/ti/
H A Ddthev2-common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * K3 DTHE V2 crypto accelerator driver
5 * Copyright (C) Texas Instruments 2025 - https://www.ti.com
6 * Author: T Pratham <t-pratham@ti.com>
16 #include <crypto/hash.h>
18 #include <crypto/internal/hash.h>
24 #include <linux/dma-mapping.h>
32 * This is currently the keysize of XTS-AES-256 which is 512 bits (64 bytes)
45 * struct dthe_data - DTHE_V2 driver instance data
67 * struct dthe_list - device data list head
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/linux/drivers/crypto/allwinner/sun4i-ss/
H A Dsun4i-ss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sun4i-ss.h - hardware cryptographic accelerator for Allwinner A20 SoC
5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
8 * Support MD5 and SHA1 hash algorithms.
29 #include <crypto/hash.h>
30 #include <crypto/internal/hash.h>
65 /* PRNG generator mode - bit 15 */
69 /* IV mode for hash */
72 /* SS operation mode - bits 12-13 */
77 /* Counter width for CNT mode - bits 10-11 */
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H A Dsun4i-ss-hash.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sun4i-ss-hash.c - hardware cryptographic accelerator for Allwinner A20 SoC
5 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
11 #include "sun4i-ss.h"
21 struct ahash_alg *alg = __crypto_ahash_alg(tfm->__crt_alg); in sun4i_hash_crainit()
27 algt = container_of(alg, struct sun4i_ss_alg_template, alg.hash); in sun4i_hash_crainit()
28 op->ss = algt->ss; in sun4i_hash_crainit()
30 err = pm_runtime_resume_and_get(op->ss->dev); in sun4i_hash_crainit()
43 pm_runtime_put(op->ss->dev); in sun4i_hash_craexit()
51 struct ahash_alg *alg = __crypto_ahash_alg(tfm->base.__crt_alg); in sun4i_hash_init()
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/linux/Documentation/security/keys/
H A Dtrusted-encrypted.rst15 It is the secure way of keeping the keys in the kernel key-ring as Trusted-Key,
18 - Key-blob, an encrypted key-data, created to be stored, loaded and seen by
20 - Key-data, the plain-key text in the system memory, to be used by
23 Though key-data is not accessible to the user-space in plain-text, but it is in
24 plain-text in system memory, when used in kernel space. Even though kernel-space
25 attracts small surface attack, but with compromised kernel or side-channel
29 In order to protect the key in kernel space, the concept of "protected-keys" is
30 introduced which will act as an added layer of protection. The key-data of the
31 protected keys is encrypted with Key-Encryption-Key(KEK), and decrypted inside
32 the trust source boundary. The plain-key text never available out-side in the
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/linux/drivers/net/ethernet/freescale/
H A Dfec.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
17 #include <dt-bindings/firmware/imx/rsrc.h>
52 #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */
53 #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash tabl
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H A Dfec_main.c1 // SPDX-License-Identifier: GPL-2.0+
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
195 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, },
196 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, },
197 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, },
198 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, },
199 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, },
200 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6sx_info, },
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/linux/drivers/net/wireless/ath/ath12k/
H A Drx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
216 * hash[3:0]} using the chosen Toeplitz hash from Common Parser
220 * {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz
221 * hash from Common Parser if flow search fails.
225 * on the chosen Toeplitz hash from Common Parser, in case
257 * field in address search failure cache-only entry should
261 * If set, intra-BSS routing detection is enabled
278 * host SW/accelerator subsystem that also handles packet
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/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/pistachio-clk.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #include <dt-bindings/reset/pistachio-resets.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_ras.h1 /* SPDX-License-Identifier: GPL-2.0-only */
51 * BIT(0) - BIT(3) - ri_iosf_pdata_rxq[0:3] parity error
52 * BIT(4) - ri_tlq_phdr parity error
53 * BIT(5) - ri_tlq_pdata parity error
54 * BIT(6) - ri_tlq_nphdr parity error
55 * BIT(7) - ri_tlq_npdata parity error
56 * BIT(8) - BIT(9) - ri_tlq_cplhdr[0:1] parity error
57 * BIT(10) - BIT(17) - ri_tlq_cpldata[0:7] parity error
58 * BIT(18) - set this bit to 1 to enable logging status to ri_mem_par_err_sts0
59 * BIT(19) - ri_cds_cmd_fifo parity error
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/linux/arch/powerpc/include/asm/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * number used in the Programming Environments Manual For 32-Bit
17 #include <asm/asm-const.h>
18 #include <asm/feature-fixups.h>
74 /* so tests for these bits fail on 32-bit */
116 #define MSR_TS_N 0 /* Non-transactional */
161 /* Power Management - Processor Stop Status and Control Register Fields */
165 #define PSSCR_PSLL_MASK 0x000F0000 /* Power-Saving Level Limit */
169 #define PSSCR_PLS 0xf000000000000000 /* Power-saving Level Status */
171 #define PSSCR_GUEST_VIS 0xf0000000000003ffUL /* Guest-visible PSSCR fields */
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/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_debugfs.c4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
57 pos -= tb->skip_first; in seq_tab_get_idx()
58 return pos >= tb->rows ? NULL : &tb->data[pos * tb->width]; in seq_tab_get_idx()
63 struct seq_tab *tb = seq->private; in seq_tab_start()
65 if (tb->skip_first && *pos == 0) in seq_tab_start()
73 v = seq_tab_get_idx(seq->private, *pos + 1); in seq_tab_next()
84 const struct seq_tab *tb = seq->private; in seq_tab_show()
86 return tb->show(seq, v, ((char *)v - tb->data) / tb->width); in seq_tab_show()
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt39 Documentation/arch/m68k/kernel-options.rst.
49 PARISC The PA-RISC architecture is enabled.
64 the Documentation/scsi/ sub-directory.
83 X86-32 X86-32, aka i386 architecture is enabled.
84 X86-64 X86-64 architecture is enabled.
85 X86 Either 32-bit or 64-bit x86 (same as X86-32+X86-64)
94 KNL Is a kernel start-up parameter.
114 force -- enable ACPI if default was off
115 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
116 off -- disable ACPI if default was on
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