Lines Matching +full:hash +full:- +full:accelerator
1 # SPDX-License-Identifier: GPL-2.0-only
39 called padlock-aes.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
76 or Accelerator (CEXxA) mode.
87 - A pkey base and API kernel module (pkey.ko) which offers the
89 and the sysfs API and the in-kernel API to the crypto cipher
91 - A pkey pckmo kernel module (pkey-pckmo.ko) which is automatically
94 - A pkey CCA kernel module (pkey-cca.ko) which is automatically
96 - A pkey EP11 kernel module (pkey-ep11.ko) which is automatically
98 - A pkey UV kernel module (pkey-uv.ko) which is automatically
202 for example to use dm-integrity with secure/protected keys.
211 and uses triple-DES to generate secure random numbers like the
212 ANSI X9.17 standard. User-space programs access the
213 pseudo-random-number device through the char device /dev/prandom.
239 tristate "Driver HIFN 795x crypto accelerator chips"
295 tristate "Driver AMCC PPC4xx crypto accelerator"
313 This option provides the kernel-side support for the TRNG hardware
326 tristate "Support for OMAP MD5/SHA1/SHA2 hw accelerator"
335 OMAP processors have MD5/SHA1/SHA2 hw accelerator. Select this if you
349 OMAP processors have AES module accelerator. Select this if you
359 OMAP processors have DES/3DES module accelerator. Select this if you
367 tristate "Support for SAHARA crypto accelerator"
374 This option enables support for the SAHARA HW crypto accelerator
383 This driver provides kernel-side support through the
388 module will be called exynos-rng.
393 tristate "Support for Samsung S5PV210/Exynos crypto accelerator"
404 bool "Support for Samsung Exynos HASH accelerator"
411 Select this to offload Exynos from HASH MD5/SHA1/SHA256.
413 needed for small and zero-size messages.
414 HASH algorithms will be disabled if EXYNOS_RNG
421 This enables support for the NX hardware cryptographic accelerator
431 bool "Support for Atmel IPSEC/SSL hw accelerator"
441 tristate "Support for Atmel AES hw accelerator"
449 Some Atmel processors have AES hw accelerator.
454 will be called atmel-aes.
457 tristate "Support for Atmel DES/TDES hw accelerator"
462 Some Atmel processors have DES/TDES hw accelerator.
467 will be called atmel-tdes.
470 tristate "Support for Atmel SHA hw accelerator"
475 hw accelerator.
480 will be called atmel-sha.
487 tristate "Support for Microchip / Atmel ECC hw accelerator"
493 Microhip / Atmel ECC hw accelerator.
498 will be called atmel-ecc.
501 tristate "Support for Microchip / Atmel SHA accelerator and RNG"
507 Microhip / Atmel SHA accelerator and RNG.
513 will be called atmel-sha204a.
537 co-processor on the die.
540 will be called mxs-dcp.
548 tristate "Qualcomm crypto engine accelerator"
552 This driver supports Qualcomm crypto engine accelerator
585 (default), hashes-only, or skciphers-only.
588 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
592 algorithms, sharing the load with the CPU. Enabling skciphers-only
602 - AES (CBC, CTR, ECB, XTS)
603 - 3DES (CBC, ECB)
604 - DES (CBC, ECB)
605 - SHA1, HMAC-SHA1
606 - SHA256, HMAC-SHA256
609 bool "Symmetric-key ciphers only"
612 Enable symmetric-key ciphers only:
613 - AES (CBC, CTR, ECB, XTS)
614 - 3DES (ECB, CBC)
615 - DES (ECB, CBC)
618 bool "Hash/HMAC only"
622 - SHA1, HMAC-SHA1
623 - SHA256, HMAC-SHA256
630 - authenc()
631 - ccm(aes)
632 - rfc4309(ccm(aes))
645 Considering the 256-bit ciphers, software is 2-3 times faster than
646 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
647 With 128-bit keys, the break-even point would be around 1024-bytes.
650 cost in CPU usage. The minimum recommended setting is 16-bytes
651 (1 AES block), since AES-GCM will fail if you set it lower.
654 Note that 192-bit keys are not supported by the hardware and are
668 module will be called qcom-rng. If unsure, say N.
679 tristate "Imagination Technologies hardware hash accelerator"
687 hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
707 This driver interfaces with the hardware crypto accelerator.
726 AES encryption/decryption and HASH algorithms.
735 Xilinx Versal SoC driver provides kernel-side support for True Random Number
736 Generator and Pseudo random Number in CTR_DRBG mode as defined in NIST SP800-90A.
739 will be called xilinx-trng.
742 tristate "Support for Xilinx ZynqMP AES hw accelerator"
748 Xilinx ZynqMP has AES-GCM engine used for symmetric key
750 accelerator. Select this if you want to use the ZynqMP module
754 tristate "Support for Xilinx ZynqMP SHA3 hardware accelerator"
758 Xilinx ZynqMP has SHA3 engine used for secure hash calculation.
761 for SHA3 hash computation.
768 tristate "Broadcom symmetric crypto/hash acceleration support"
801 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
804 SHA384 and SHA512 hash algorithms for both basic hash and HMAC.
805 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
808 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
821 Enables the driver for the on-chip crypto accelerator
861 tristate "Support for TI security accelerator"
873 K3 devices include a security accelerator engine that may be
879 source "drivers/crypto/inside-secure/eip93/Kconfig"