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/linux/tools/perf/pmu-events/arch/riscv/
H A Driscv-sbi-firmware.json39 "PublicDescription": "Sent IPI to other HART event",
42 "BriefDescription": "Sent IPI to other HART event"
45 "PublicDescription": "Received IPI from other HART event",
48 "BriefDescription": "Received IPI from other HART event"
51 "PublicDescription": "Sent FENCE.I request to other HART event",
54 "BriefDescription": "Sent FENCE.I request to other HART event"
57 "PublicDescription": "Received FENCE.I request from other HART event",
60 "BriefDescription": "Received FENCE.I request from other HART event"
63 "PublicDescription": "Sent SFENCE.VMA request to other HART event",
66 "BriefDescription": "Sent SFENCE.VMA request to other HART event"
[all …]
/linux/arch/riscv/kernel/
H A Dcpu.c27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
30 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
34 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
35 if (*hart == ~0UL) { in riscv_of_processor_hartid()
36 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
40 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
50 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_early_of_processor_hartid() argument
59 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid()
60 if (*hart == ~0UL) { in riscv_early_of_processor_hartid()
[all …]
H A Dsmpboot.c73 unsigned long hart; in acpi_parse_rintc() local
90 hart = processor->hart_id; in acpi_parse_rintc()
91 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
96 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
107 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc()
124 unsigned long hart; in of_parse_and_init_cpus() local
130 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus()
134 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus()
142 cpuid, hart); in of_parse_and_init_cpus()
146 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
[all …]
H A Dhead.S174 * Park this hart if we:
249 /* Pick one hart to run the main boot sequence */
347 * This hart didn't win the lottery, so we wait for the winning hart to
H A Dkexec_relocate.S19 * s3: (const) The hartid of the current hart
155 * s2: (const) The hartid of the current hart
/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74115.yaml70 10 - Current output with HART
71 11 - Current input, externally-powered, with HART
72 12 - Current input, loop-powered, with HART
188 adi,dac-hart-slew:
190 description: Whether to use a HART-compatible slew rate.
268 3 - Control HART CD
269 4 - Monitor HART CD
270 5 - Monitor HART EOM status
282 3 - Control HART RXD
283 4 - Monitor HART RXD
[all …]
H A Dadi,ad74413r.yaml20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
81 HART functions are not supported on AD74412R.
/linux/arch/riscv/mm/
H A Dcacheflush.c39 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
42 * execution resumes on each hart.
51 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
54 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
68 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
69 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
71 * messages are sent we still need to order this hart's writes in flush_icache_mm()
166 * Mark every other hart's icache as needing a flush for in set_icache_stale_mask()
210 * process is migrated, the corresponding hart's icache will be guaranteed to be
219 * instructions. When the thread is migrated, the corresponding hart's icache
/linux/drivers/irqchip/
H A Dirq-riscv-intc.c48 * on the local hart, these functions can only be called on the hart that
97 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi()
99 * chained handlers for the per-HART local interrupts. in riscv_intc_irq_eoi()
103 * will do unnecessary mask/unmask of per-HART local interrupts in riscv_intc_irq_eoi()
218 pr_warn("unable to find hart id for %pOF\n", node); in riscv_intc_init()
223 * The DT will have one INTC DT node under each CPU (or HART) in riscv_intc_init()
226 * for the INTC DT node belonging to boot CPU (or boot HART). in riscv_intc_init()
368 * The ACPI MADT will have one INTC for each CPU (or HART) in riscv_intc_acpi_init()
371 * for the INTC belonging to the boot CPU (or boot HART). in riscv_intc_acpi_init()
H A Dirq-riscv-aplic-msi.c103 /* Compute target HART Base PPN */ in aplic_msi_write_msg()
110 /* Compute target group and hart indexes */ in aplic_msi_write_msg()
212 /* Find number of HART index bits (LHXW) */ in aplic_msi_setup()
215 dev_err(dev, "IMSIC hart index bits big for APLIC LHXW\n"); in aplic_msi_setup()
/linux/arch/csky/abiv2/
H A Dcacheflush.c47 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
71 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.yaml7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
/linux/arch/riscv/include/asm/
H A Dcpu_ops_sbi.h16 * struct sbi_hart_boot_data - Hart specific boot used during booting and
18 * @task_ptr: A pointer to the hart specific tp
19 * @stack_ptr: A pointer to the hart specific sp
H A Dbarrier.h51 * task is marked as available for scheduling on a new hart. While I don't see
55 * the new hart.
H A Dkvm_aia.h39 /* Number of hart bits in IMSIC address */
72 /* HART index of IMSIC extacted from guest physical address */
/linux/Documentation/arch/riscv/
H A Duabi.rst45 "isa" and "hart isa" lines in /proc/cpuinfo
50 "hart isa" line, in contrast, describes the set of extensions recognized by the
51 kernel on the particular hart being described, even if those extensions may not
/linux/tools/testing/selftests/futex/
H A Drun.sh13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
/linux/tools/arch/riscv/include/uapi/asm/
H A Dunistd.h29 * kernel might schedule a process on another hart. There is no way for
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
/linux/include/linux/irqchip/
H A Driscv-imsic.h53 * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
57 /* Bits representing Guest index, HART index, and Group index */
/linux/tools/testing/selftests/futex/functional/
H A Drun.sh12 # Darren Hart <dvhart@linux.intel.com>
15 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
H A Dfutex_requeue_pi_mismatched_ops.c12 * Darren Hart <dvhart@linux.intel.com>
15 * 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
/linux/tools/testing/selftests/futex/include/
H A Datomic.h11 * Darren Hart <dvhart@linux.intel.com>
14 * 2009-Nov-17: Initial version by Darren Hart <dvhart@linux.intel.com>
H A Dlogging.h10 * Darren Hart <dvhart@linux.intel.com>
13 * 2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>
/linux/arch/riscv/kvm/
H A Daia_device.c240 u32 hart = 0, group = 0; in aia_imsic_hart_index() local
243 hart = (addr >> (aia->nr_guest_bits + IMSIC_MMIO_PAGE_SHIFT)) & in aia_imsic_hart_index()
249 return (group << aia->nr_hart_bits) | hart; in aia_imsic_hart_index()
300 /* Update HART index of the IMSIC based on IMSIC base */ in aia_init()
/linux/arch/riscv/purgatory/
H A Dentry.S18 mv s0, a0 /* The hartid of the current hart */

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