Home
last modified time | relevance | path

Searched +full:hart +full:- +full:1 (Results 1 – 25 of 51) sorted by relevance

123

/linux/arch/riscv/kernel/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
30 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
34 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
35 if (*hart == ~0UL) { in riscv_of_processor_hartid()
36 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
37 return -ENODEV; in riscv_of_processor_hartid()
40 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
[all …]
H A Dsmpboot.c1 // SPDX-License-Identifier: GPL-2.0-only
56 /* This covers non-smp usecase mandated by "nosmp" option */ in smp_prepare_cpus()
69 static unsigned int cpu_count = 1;
73 unsigned long hart; in acpi_parse_rintc() local
82 if (!(processor->flags & ACPI_MADT_ENABLED)) in acpi_parse_rintc()
86 return -EINVAL; in acpi_parse_rintc()
88 acpi_table_print_madt_entry(&header->common); in acpi_parse_rintc()
90 hart = processor->hart_id; in acpi_parse_rintc()
91 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
96 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
[all …]
H A Dmachine_kexec.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 FORTH-ICS/CARV
22 * machine_kexec_prepare - Initialize kexec
33 struct kimage_arch *internal = &image->arch; in machine_kexec_prepare()
40 for (i = 0; i < image->nr_segments; i++) { in machine_kexec_prepare()
41 if (image->segment[i].memsz <= sizeof(fdt)) in machine_kexec_prepare()
44 if (image->file_mode) in machine_kexec_prepare()
45 memcpy(&fdt, image->segment[i].buf, sizeof(fdt)); in machine_kexec_prepare()
46 else if (copy_from_user(&fdt, image->segment[i].buf, sizeof(fdt))) in machine_kexec_prepare()
52 internal->fdt_addr = (unsigned long) image->segment[i].mem; in machine_kexec_prepare()
[all …]
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-only */
6 #include <asm/asm-offsets.h>
18 #include "efi-header.S"
23 * Image header expected by Linux boot-loaders. The image header data
32 c.li s4,-13
42 /* Image load offset (0MB) from start of RAM for M-mode */
54 .dword _end - _start
63 .word pe_head_start - _start
84 la a2, 1f
108 1:
[all …]
H A Dkexec_relocate.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2019 FORTH-ICS/CARV
19 * s3: (const) The hartid of the current hart
45 la s6, 1f
50 * With C-extension, here we get 42 Bytes and the next
58 1:
59 REG_L t0, 0(s0) /* t0 = *image->entry */
60 addi s0, s0, RISCV_SZPTR /* image->entry++ */
62 /* IND_DESTINATION entry ? -> save destination address */
66 j 1b
[all …]
/linux/Documentation/devicetree/bindings/iio/addac/
H A Dadi,ad74115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74115H is a single-channel software configurable input/output
17 chip solution with an SPI interface. The device features a 16-bit ADC and a
18 14-bit DAC.
25 - adi,ad74115h
28 maxItems: 1
30 spi-max-frequency:
[all …]
H A Dadi,ad74413r.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cosmin Tanislav <cosmin.tanislav@analog.com>
13 The AD74412R and AD74413R are quad-channel software configurable input/output
18 The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide
20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
27 - adi,ad74412r
28 - adi,ad74413r
31 maxItems: 1
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dthead,c900-aclint-sswi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ACLINT Supervisor-level Software Interrupt Device
10 - Inochi Amaoto <inochiama@outlook.com>
14 supervisor-level IPI functionality for a set of HARTs on a supported
16 HART connected to the SSWI device. See draft specification
17 https://github.com/riscvarchive/riscv-aclint
21 - THEAD C900
[all …]
H A Driscv,cpu-intc.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
10 RISC-V cores include Control Status Registers (CSRs) which are local to
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
[all …]
/linux/arch/riscv/mm/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0-only
30 * the IPI. The RISC-V spec states that a hart must execute a data fence in flush_icache_all()
34 * IPIs on RISC-V are triggered by MMIO writes to either CLINT or in flush_icache_all()
35 * S-IMSIC, so the fence ensures previous data writes "happen before" in flush_icache_all()
43 on_each_cpu(ipi_remote_fence_i, NULL, 1); in flush_icache_all()
48 * Performs an icache flush for the given MM context. RISC-V has no direct
52 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
55 * execution resumes on each hart.
64 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
65 mask = &mm->context.icache_stale_mask; in flush_icache_mm()
[all …]
H A Dcontext.c1 // SPDX-License-Identifier: GPL-2.0
87 /* Mark ASID #0 as used because it is used at boot-time */ in __flush_context()
90 /* Queue a TLB invalidation for each CPU on next context-switch */ in __flush_context()
96 static u32 cur_idx = 1; in __new_context()
97 unsigned long cntx = atomic_long_read(&mm->context.id); in __new_context()
115 * re-use it if possible. in __new_context()
136 asid = find_next_zero_bit(context_asid_map, num_asids, 1); in __new_context()
150 cntx = atomic_long_read(&mm->context.id); in set_mm_asid()
153 * If our active_context is non-zero and the context matches the in set_mm_asid()
159 * - We get a zero back from the cmpxchg and end up waiting on the in set_mm_asid()
[all …]
/linux/drivers/irqchip/
H A Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
31 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
46 * On RISC-V systems local interrupts are masked or unmasked by writing
48 * on the local hart, these functions can only be called on the hart that
54 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_mask()
55 csr_clear(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_mask()
57 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
62 if (IS_ENABLED(CONFIG_32BIT) && d->hwirq >= BITS_PER_LONG) in riscv_intc_irq_unmask()
[all …]
H A Dirq-riscv-aplic-msi.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/irqchip/riscv-aplic.h>
13 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-aplic-main.h"
43 * The section "4.9.2 Special consideration for level-sensitive interrupt in aplic_msi_irq_retrigger_level()
44 * sources" of the RISC-V AIA specification says: in aplic_msi_irq_retrigger_level()
52 writel(d->hwirq, priv->regs + APLIC_SETIPNUM_LE); in aplic_msi_irq_retrigger_level()
60 * EOI handling is required only for level-triggered interrupts in aplic_msi_irq_eoi()
73 * Updating sourcecfg register for level-triggered interrupts in aplic_msi_irq_set_type()
84 struct aplic_msicfg *mc = &priv->msicfg; in aplic_msi_write_msg()
[all …]
/linux/arch/csky/abiv2/
H A Dcacheflush.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
24 if (test_and_set_bit(PG_dcache_clean, &folio->flags.f)) in update_mmu_cache_range()
33 if (vma->vm_flags & VM_EXEC) in update_mmu_cache_range()
42 cpumask_t *mask = &mm->context.icache_stale_mask; in flush_icache_deferred()
47 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
64 if (mm == current->mm) { in flush_icache_mm_range()
71 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
72 mask = &mm->context.icache_stale_mask; in flush_icache_mm_range()
75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
[all …]
/linux/Documentation/arch/riscv/
H A Dcmodx.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Concurrent Modification and Execution of Instructions (CMODX) for RISC-V Linux
9 (icache) are not guaranteed to be synchronized on RISC-V hardware. Therefore, the
14 -------------------------
17 ---------------------
21 enable or disable the redirection. In the case of RISC-V, 2 instructions,
23 to patch 2 instructions and expect that a concurrent read-side executes them
25 RISC-V ftrace. Kernel preemption makes things even worse as it allows the old
29 preemption, we partially initialize each patchable function entry at boot-time,
36 is limited to +-2K from the predetermined target, ftrace_caller, due to the lack
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dandestech,plmt0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Andes machine-level timer
10 The Andes machine-level timer device (PLMT0) provides machine-level timer
11 functionality for a set of HARTs on a RISC-V platform. It has a single
12 fixed-frequency monotonic time counter (MTIME) register and a time compare
13 register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is
17 - Ben Zong-You Xie <ben717@andestech.com>
22 - enum:
[all …]
/linux/tools/testing/selftests/futex/
H A Drun.sh2 # SPDX-License-Identifier: GPL-2.0-or-later
13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
23 if [ $? -eq 0 ]; then
24 USE_COLOR=1
/linux/tools/testing/selftests/futex/include/
H A Datomic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 * http://gcc.gnu.org/onlinedocs/gcc-4.1.0/gcc/Atomic-Builtins.html
11 * Darren Hart <dvhart@linux.intel.com>
14 * 2009-Nov-17: Initial version by Darren Hart <dvhart@linux.intel.com>
28 * atomic_cmpxchg() - Atomic compare and exchange
33 * Return the old value of addr->val.
38 return __sync_val_compare_and_swap(&addr->val, oldval, newval); in atomic_cmpxchg()
42 * atomic_inc() - Atomic incrememnt
45 * Return the new value of addr->val.
50 return __sync_add_and_fetch(&addr->val, 1); in atomic_inc()
[all …]
/linux/include/linux/irqchip/
H A Driscv-imsic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
50 * XLEN-1 12 0
52 * -------------------------------------------------------------
53 * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
54 * -------------------------------------------------------------
57 /* Bits representing Guest index, HART index, and Group index */
72 /* Per-CPU IMSIC addresses */
/linux/tools/testing/selftests/futex/functional/
H A Dfutex_requeue_pi_mismatched_ops.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * 1. Block a thread using FUTEX_WAIT
8 * 2. Attempt to use FUTEX_CMP_REQUEUE_PI on the futex from 1.
9 * 3. The kernel must detect the mismatch and return -EINVAL.
12 * Darren Hart <dvhart@linux.intel.com>
15 * 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
38 child_ret = -errno; in blocking_child()
53 sleep(1); in TEST()
57 * q->requeue_pi_key and return -EINVAL. If it does not, in TEST()
61 ret = futex_cmp_requeue_pi(&f1, f1, &f2, 1, 0, FUTEX_PRIVATE_FLAG); in TEST()
[all …]
H A Dfutex_requeue_pi_signal_restart.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright © International Business Machines Corp., 2006-2008
12 * Darren Hart <dvhart@linux.intel.com>
15 * 2008-May-5: Initial version by Darren Hart <dvhart@linux.intel.com>
113 res = create_rt_thread(&waiter, waiterfn, NULL, SCHED_FIFO, 1); in TEST()
122 while (1) { in TEST()
134 res = futex_cmp_requeue_pi(&f1, old_val, &(f2), 1, 0, in TEST()
137 * If res is non-zero, we either requeued the waiter or hit an in TEST()
143 atomic_set(&requeued, 1); in TEST()
H A Dfutex_wait_timeout.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * Darren Hart <dvhart@linux.intel.com>
13 * 2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>
14 * 2021-Apr-26: More test cases by André Almeida <andrealmeid@collabora.com>
72 to->tv_nsec += timeout_ns; in futex_get_abs_timeout()
74 if (to->tv_nsec >= 1000000000) { in futex_get_abs_timeout()
75 to->tv_sec++; in futex_get_abs_timeout()
76 to->tv_nsec -= 1000000000; in futex_get_abs_timeout()
98 res = futex_wait_bitset(&f1, f1, &to, 1, FUTEX_CLOCK_REALTIME); in TEST()
104 res = futex_wait_bitset(&f1, f1, &to, 1, 0); in TEST()
[all …]
/linux/arch/riscv/include/asm/
H A Dkvm_aia.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 /* In-kernel irqchip created */
21 /* In-kernel irqchip initialized */
39 /* Number of hart bits in IMSIC address */
69 /* HART index of IMSIC extacted from guest physical address */
76 #define KVM_RISCV_AIA_UNDEF_ADDR (-1)
78 #define kvm_riscv_aia_initialized(k) ((k)->arch.aia.initialized)
80 #define irqchip_in_kernel(k) ((k)->arch.aia.in_kernel)
96 #define KVM_RISCV_AIA_IMSIC_TOPEI (ISELECT_MASK + 1)
148 { .base = CSR_SIREG, .count = 1, .func = kvm_riscv_vcpu_aia_rmw_ireg }, \
[all …]
/linux/arch/riscv/kvm/
H A Daia_device.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/irqchip/riscv-imsic.h>
19 struct kvm *kvm = dev->kvm; in aia_create()
23 return -EEXIST; in aia_create()
25 ret = -EBUSY; in aia_create()
30 if (vcpu->arch.ran_atleast_once) in aia_create()
35 kvm->arch.aia.in_kernel = true; in aia_create()
50 struct kvm_aia *aia = &kvm->arch.aia; in aia_config()
54 return -EBUSY; in aia_config()
66 * supported on host with non-zero guest in aia_config()
[all …]
/linux/drivers/cpuidle/
H A Dcpuidle-riscv-sbi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * RISC-V SBI CPU idle driver.
9 #define pr_fmt(fmt) "cpuidle-riscv-sbi: " fmt
52 data->available = true; in sbi_set_domain_state()
53 data->state = state; in sbi_set_domain_state()
60 return data->state; in sbi_get_domain_state()
67 data->available = false; in sbi_clear_domain_state()
74 return data->available; in sbi_is_domain_state_available()
95 u32 *states = data->states; in __sbi_enter_domain_idle_state()
96 struct device *pd_dev = data->dev; in __sbi_enter_domain_idle_state()
[all …]

123