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Searched +full:hart +full:- +full:1 (Results 1 – 25 of 68) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A D	microchip,sbi-ipc.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mailbox/microchip,sbi-ipc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip Inter-processor communication (IPC) mailbox controller 10 - Valentina Fernandez <valentina.fernandezalanis@microchip.com> 13 The Microchip Inter-processor Communication (IPC) facilitates 20 - description: 22 mode (s-mode). This SBI interface is compatible with the Mi-V 23 Inter-hart Communication (IHC) IP. [all …]
/freebsd/sys/contrib/device-tree/Bindings/iio/addac/
H A D	adi,ad74115.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...]`
H A D	adi,ad74413r.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Cosmin Tanislav <cosmin.tanislav@analog.com> 13 The AD74412R and AD74413R are quad-channel software configurable input/output 18 The devices feature a 16-bit ADC and four configurable 13-bit DACs to provide 20 The AD74413R differentiates itself from the AD74412R by being HART-compatible. 27 - adi,ad74412r 28 - adi,ad74413r 31 maxItems: 1 [all …]`
/freebsd/sys/riscv/riscv/
H A D	mp_machdep.c	1 /- 11 FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 20 * 1. Redistributions of source code must retain the above copyright 107 /* Set to 1 once we're ready to let the APs out of the pen. / 111 void dpcpu[MAXCPU - 1]; 119 if (mp_ncpus == 1) in release_aps() 130 atomic_store_rel_int(&aps_ready, 1); in release_aps() 151 init_secondary(uint64_t hart) in init_secondary() argument 157 cpuid = hart; in init_secondary() 159 cpuid += mp_maxid + 1; in init_secondary() [all …]
H A D	plic.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 10 * and Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of 16 * 1. Redistributions of source code must retain the above copyright 52 #include <dt-bindings/interrupt-controller/irq.h> 70 (_sc->contexts[_cpu].enable_offset + ((_irq) / 32) * sizeof(uint32_t)) 72 (_sc->contexts[_cpu].context_offset + PLIC_CONTEXT_THRESHOLD) 74 (_sc->contexts[_cpu].context_offset + PLIC_CONTEXT_CLAIM) 106 { "riscv,plic0", 1 }, 107 { "sifive,plic-1.0.0", 1 }, [all …]
H A D	identcpu.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com> 11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 23 * 1. Redistributions of source code must retain the above copyright 76 /* Supervisor-mode extension support. / 82 / Z-extensions support. / 90 u_int isa_extensions; / Single-letter extensions. */ 93 #define SV_SSTC (1 << 0) 94 #define SV_SVNAPOT (1 << 1) [all …]`
H A D	machdep.c	1 /- 3 Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 17 * 1. Redistributions of source code must retain the above copyright 109 int early_boot = 1; 110 int cold = 1; 117 uint32_t boot_hart = BOOT_HART_INVALID; /* The hart we booted on. */ 142 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { in cpu_startup() 145 size = phys_avail[indx + 1] - phys_avail[indx]; in cpu_startup() 147 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", in cpu_startup() [all …]
H A D	sbi.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 10 * 1. Redistributions of source code must retain the above copyright 41 /* SBI Implementation-Specific Definitions */ 145 printf("SBI: Kernel-based Virtual Machine %lu\n", in sbi_print_version() 161 printf("SBI: PolarFire Hart Software Services %lu\n", in sbi_print_version() 263 sbi_hsm_hart_start(u_long hart, u_long start_addr, u_long priv) in sbi_hsm_hart_start() argument 267 ret = SBI_CALL3(SBI_EXT_ID_HSM, SBI_HSM_HART_START, hart, start_addr, in sbi_hsm_hart_start() 279 sbi_hsm_hart_status(u_long hart) in sbi_hsm_hart_status() argument 283 ret = SBI_CALL1(SBI_EXT_ID_HSM, SBI_HSM_HART_STATUS, hart); in sbi_hsm_hart_status() [all …]
H A D	aplic.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 9 * 1. Redistributions of source code must retain the above copyright 51 #define APLIC_INTR_DEF_PRIO 1 71 struct aplic_irqsrc isrcs[APLIC_MAX_IRQS + 1]; 76 #define APLIC_DOMAIN_CFG_IE (1UL << 8) /* Enable domain IRQs / 77 #define APLIC_DOMAIN_CFG_DM (1UL << 2) / IRQ delivery mode / 78 #define APLIC_DOMAIN_CFG_BE (1UL << 0) / Endianess / 81 #define APLIC_MODE_MSI 1 / MSI delivery mode / 83 #define APLIC_SRC_CFG_DLGT (1UL << 10) / Source delegation */ [all …]
H A D	locore.S	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> 6 * Copyright (c) 2019-2021 Mitchell Horne <mhorne@FreeBSD.org> 7 * Copyright (c) 2022-2024 The FreeBSD Foundation 11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 23 * 1. Redistributions of source code must retain the above copyright 58 * - a0 = hart ID 59 * - a1 = dtbp 61 * Multiple CPUs might enter from this point, so we perform a hart lottery and [all …]`
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A D	thead,c900-aclint-sswi.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ACLINT Supervisor-level Software Interrupt Device 10 - Inochi Amaoto <inochiama@outlook.com> 14 supervisor-level IPI functionality for a set of HARTs on a supported 16 HART connected to the SSWI device. See draft specification 17 https://github.com/riscvarchive/riscv-aclint 21 - THEAD C900 [all …]
H A D	riscv,cpu-intc.txt	1 RISC-V Hart-Level Interrupt Controller (HLIC) 2 --------------------------------------------- 4 RISC-V cores include Control Status Registers (CSRs) which are local to each 5 CPU core (HART in RISC-V terminology) and can be read or written by software. 7 Every interrupt is ultimately routed through a hart's HLIC before it 8 interrupts that hart. 10 The RISC-V supervisor ISA manual specifies three interrupt sources that are 13 timer interrupt comes from an architecturally mandated real-time timer that is 16 via the platform-level interrupt controller (PLIC). 18 All RISC-V systems that conform to the supervisor ISA specification are [all …]
H A D	riscv,imsics.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V Incoming MSI Controller (IMSIC) 10 - Anup Patel <anup@brainfault.org> 13 The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming 14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V 15 AIA specification can be found at https://github.com/riscv/riscv-aia. 17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file [all …]
H A D	riscv,cpu-intc.yaml	1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V Hart-Level Interrupt Controller (HLIC) 10 RISC-V cores include Control Status Registers (CSRs) which are local to 11 each CPU core (HART in RISC-V terminology) and can be read or written by 13 to the core. Every interrupt is ultimately routed through a hart's HLIC 14 before it interrupts that hart. 16 The RISC-V supervisor ISA manual specifies three interrupt sources that are [all …]
H A D	sifive,plic-1.0.0.txt	1 SiFive Platform-Level Interrupt Controller (PLIC) 2 ------------------------------------------------- 4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller 5 (PLIC) high-level specification in the RISC-V Privileged Architecture 7 hart contexts in the system, via the external interrupt source in each hart. 9 A hart context is a privilege mode in a hardware execution thread. For example, 10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 11 privilege modes per hart; machine mode and supervisor mode. 13 Each interrupt can be enabled on per-context basis. Any context can claim 21 While the PLIC supports both edge-triggered and level-triggered interrupts, [all …]
H A D	riscv,aplic.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC) 10 - Anup Patel <anup@brainfault.org> 13 The RISC-V advanced interrupt architecture (AIA) defines an advanced 15 in a RISC-V platform. The RISC-V AIA specification can be found at 16 https://github.com/riscv/riscv-aia. 18 The RISC-V APLIC is implemented as hierarchical APLIC domains where all [all …]
H A D	sifive,plic-1.0.0.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 4 --- 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: SiFive Platform-Level Interrupt Controller (PLIC) 11 SiFive SoCs and other RISC-V SoCs include an implementation of the 12 Platform-Level Interrupt Controller (PLIC) high-level specification in 13 the RISC-V Privileged Architecture specification. The PLIC connects all 14 external interrupts in the system to all hart contexts in the system, via 15 the external interrupt source in each hart. [all …]
/freebsd/sys/riscv/include/
H A D	sbi.h	`1 /- 2 Copyright (c) 2016-2017 Ruslan Bukin <br@bsdpad.com> 8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 17 * 1. Redistributions of source code must retain the above copyright 47 #define SBI_IMPL_ID_OPENSBI 1 61 #define SBI_ERR_FAILURE -1 62 #define SBI_ERR_NOT_SUPPORTED -2 63 #define SBI_ERR_INVALID_PARAM -3 64 #define SBI_ERR_DENIED -4 65 #define SBI_ERR_INVALID_ADDRESS -5 [all …]`
/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A D	cpus.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V CPUs 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 15 This document uses some terminology common to the RISC-V community 18 hart: A hardware execution context, which contains all the state 19 mandated by the RISC-V ISA: a PC and some registers. This [all …]`
H A D	extensions.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V ISA extensions 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others 18 This document defines properties that indicate whether a hart supports a [all …]`
/freebsd/sys/contrib/device-tree/Bindings/timer/
H A D	andestech,plmt0.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Andes machine-level timer 10 The Andes machine-level timer device (PLMT0) provides machine-level timer 11 functionality for a set of HARTs on a RISC-V platform. It has a single 12 fixed-frequency monotonic time counter (MTIME) register and a time compare 13 register (MTIMECMP) for each HART connected to the PLMT0. A timer interrupt is 17 - Ben Zong-You Xie <ben717@andestech.com> 22 - enum: [all …]
/freebsd/contrib/ntp/sntp/
H A D	COPYRIGHT	`6 Last update: 7-Jan-2024 00:29 UTC 15 * Copyright (c) University of Delaware 1992-2015 * 32 Hart, Danny Mayer, Martin Burnicki, and possibly others is: 35 * Copyright (c) Network Time Foundation 2011-2024 * 42 * 1. Redistributions of source code must retain the above copyright * 66 1. [1]Takao Abe <takao_abe@xurb.jp> Clock driver for JJY receivers 70 and PCI-bus devices 82 11. [12]Jean-Francoi [all...]`
/freebsd/contrib/ntp/
H A D	COPYRIGHT	`6 Last update: 7-Jan-2024 00:29 UTC 15 * Copyright (c) University of Delaware 1992-2015 * 32 Hart, Danny Mayer, Martin Burnicki, and possibly others is: 35 * Copyright (c) Network Time Foundation 2011-2024 * 42 * 1. Redistributions of source code must retain the above copyright * 66 1. [1]Takao Abe <takao_abe@xurb.jp> Clock driver for JJY receivers 70 and PCI-bus devices 82 11. [12]Jean-Francoi [all...]`
H A D	NEWS	`1 --- 10 - changes crypto (OpenSSL or compatible) detection and default build behavior. 11 Previously, crypto was supported if available unless the --without-crypto 13 falling back to a crypto-free build if usable libcrypto was not found has 15 The --withou [all...]`
/freebsd/usr.sbin/bhyve/riscv/
H A D	bhyverun_machdep.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 16 * 1. Redistributions of source code must retain the above copyright 66 #define UART_INTR 1 95 "Usage: %s [-CDHhSW]\n" in bhyve_usage() 96 " %s [-c [[cpus=]numcpus][,sockets=n][,cores=n][,threads=n]]\n" in bhyve_usage() 97 " %s [-k config_file] [-m mem] [-o var=value]\n" in bhyve_usage() 98 " %*s [-p vcpu:hostcpu] [-r file] [-s pci] [-U uuid] vmname\n" in bhyve_usage() 99 " -C: include guest memory in core file\n" in bhyve_usage() 100 " -c: number of CPUs and/or topology specification\n" in bhyve_usage() [all …]

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