Lines Matching +full:hart +full:- +full:1
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19 privilege modes per hart; machine mode and supervisor mode.
21 Each interrupt can be enabled on per-context basis. Any context can claim
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44 T-HEAD PLIC implementation requires setting a delegation bit to allow access
45 from S-mode. So add thead,c900-plic to distinguish them.
48 - Paul Walmsley <paul.walmsley@sifive.com>
49 - Palmer Dabbelt <palmer@dabbelt.com>
54 - items:
55 - enum:
56 - andestech,qilai-plic
57 - renesas,r9a07g043-plic
58 - const: andestech,nceplic100
59 - items:
60 - enum:
61 - canaan,k210-plic
62 - sifive,fu540-c000-plic
63 - spacemit,k1-plic
64 - starfive,jh7100-plic
65 - starfive,jh7110-plic
66 - const: sifive,plic-1.0.0
67 - items:
68 - enum:
69 - allwinner,sun20i-d1-plic
70 - sophgo,cv1800b-plic
71 - sophgo,cv1812h-plic
72 - sophgo,sg2002-plic
73 - sophgo,sg2042-plic
74 - sophgo,sg2044-plic
75 - thead,th1520-plic
76 - const: thead,c900-plic
77 - items:
78 - const: sifive,plic-1.0.0
79 - const: riscv,plic0
84 maxItems: 1
86 '#address-cells':
89 '#interrupt-cells': true
91 interrupt-controller: true
93 interrupts-extended:
94 minItems: 1
97 Specifies which contexts are connected to the PLIC, with "-1" specifying
99 riscv,cpu-intc node, which has a riscv node as parent.
108 power-domains: true
113 - compatible
114 - '#address-cells'
115 - '#interrupt-cells'
116 - interrupt-controller
117 - reg
118 - interrupts-extended
119 - riscv,ndev
122 - if:
127 - andestech,nceplic100
128 - thead,c900-plic
132 '#interrupt-cells':
137 '#interrupt-cells':
138 const: 1
140 - if:
144 const: renesas,r9a07g043-plic
149 maxItems: 1
151 power-domains:
152 maxItems: 1
155 maxItems: 1
158 - clocks
159 - power-domains
160 - resets
165 - |
166 plic: interrupt-controller@c000000 {
167 #address-cells = <0>;
168 #interrupt-cells = <1>;
169 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
170 interrupt-controller;
171 interrupts-extended = <&cpu0_intc 11>,