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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,gsbi.txt1 QCOM GSBI (General Serial Bus Interface) Driver
3 The GSBI controller is modeled as a node with zero or more child nodes, each
4 representing a serial sub-node device that is mux'd as part of the GSBI
6 the 4 GSBI IOs.
9 - compatible: Should contain "qcom,gsbi-v1.0.0"
10 - cell-index: Should contain the GSBI index
11 - reg: Address range for GSBI registers
12 - clocks: required clock
13 - clock-names: must contain "iface" entry
14 - qcom,mode : indicates MUX value for configuration of the serial interface.
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H A Dqcom,gsbi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm General Serial Bus Interface (GSBI)
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The GSBI controller is modeled as a node with zero or more child nodes, each
16 representing a serial sub-node device that is mux'd as part of the GSBI
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8660.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dqcom-mdm9615.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm961
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H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rp
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H A Dqcom-msm8960.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm896
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H A Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-binding
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H A Dqcom-ipq8064-v1.0.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-ipq8064.dtsi"
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/leds/common.h>
7 model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
14 stdout-path = "serial0:115200n8";
17 gpio-key
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H A Dqcom-ipq8064-ap148.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-ipq8064-v1.0.dtsi"
5 model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
6 compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
13 drive-strength = <2>;
14 bias-pull-up;
19 gsbi@16300000 {
22 clock-frequency = <200000>;
23 pinctrl-0 = <&i2c4_pins>;
24 pinctrl-names = "default";
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dqcom,msm-uartdm.txt3 The MSM serial UARTDM hardware is designed for high-speed use cases where the
4 transmit and/or receive channels can be offloaded to a dma-engine. From a
9 - compatible: Should contain at least "qcom,msm-uartdm".
12 "qcom,msm-uartdm-v1.1"
13 "qcom,msm-uartdm-v1.2"
14 "qcom,msm-uartdm-v1.3"
15 "qcom,msm-uartdm-v1.4"
16 - reg: Should contain UART register locations and lengths. The first
18 register location shall specify the GSBI control region.
19 "qcom,msm-uartdm-v1.3" is the only compatible value that might
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H A Dqcom,msm-uartdm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
5 $schema: http://devicetree.org/meta-schema
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