Lines Matching +full:gsbi +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
13 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
15 #include <dt-bindings/mfd/qcom-rpm.h>
16 #include <dt-bindings/soc/qcom,gsbi.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
23 interrupt-parent = <&intc>;
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a5";
33 next-level-cache = <&L2>;
37 cpu-pmu {
38 compatible = "arm,cortex-a5-pmu";
44 compatible = "fixed-clock";
45 #clock-cells = <0>;
46 clock-frequency = <19200000>;
50 vsdcc_fixed: vsdcc-regulator {
51 compatible = "regulator-fixed";
52 regulator-name = "SDCC Power";
53 regulator-min-microvolt = <2700000>;
54 regulator-max-microvolt = <2700000>;
55 regulator-always-on;
59 #address-cells = <1>;
60 #size-cells = <1>;
62 compatible = "simple-bus";
64 L2: cache-controller@2040000 {
65 compatible = "arm,pl310-cache";
67 arm,data-latency = <2 2 0>;
68 cache-unified;
69 cache-level = <2>;
72 intc: interrupt-controller@2000000 {
73 compatible = "qcom,msm-qgic2";
74 interrupt-controller;
75 #interrupt-cells = <3>;
81 compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer",
82 "qcom,msm-timer";
87 clock-frequency = <27000000>;
88 cpu-offset = <0x80000>;
92 compatible = "qcom,mdm9615-pinctrl";
93 gpio-controller;
94 gpio-ranges = <&msmgpio 0 0 88>;
95 #gpio-cells = <2>;
97 interrupt-controller;
98 #interrupt-cells = <2>;
102 gcc: clock-controller@900000 {
103 compatible = "qcom,gcc-mdm9615";
104 #clock-cells = <1>;
105 #power-domain-cells = <1>;
106 #reset-cells = <1>;
112 lcc: clock-controller@28000000 {
113 compatible = "qcom,lcc-mdm9615";
115 #clock-cells = <1>;
116 #reset-cells = <1>;
123 clock-names = "cxo",
133 l2cc: clock-controller@2011000 {
134 compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
142 clock-names = "core";
143 assigned-clocks = <&gcc PRNG_CLK>;
144 assigned-clock-rates = <32000000>;
147 gsbi2: gsbi@16100000 {
148 compatible = "qcom,gsbi-v1.0.0";
149 cell-index = <2>;
152 clock-names = "iface";
154 #address-cells = <1>;
155 #size-cells = <1>;
159 compatible = "qcom,i2c-qup-v1.1.1";
160 #address-cells = <1>;
161 #size-cells = <0>;
166 clock-names = "core", "iface";
171 gsbi3: gsbi@16200000 {
172 compatible = "qcom,gsbi-v1.0.0";
173 cell-index = <3>;
176 clock-names = "iface";
178 #address-cells = <1>;
179 #size-cells = <1>;
183 compatible = "qcom,spi-qup-v1.1.1";
184 #address-cells = <1>;
185 #size-cells = <0>;
190 clock-names = "core", "iface";
195 gsbi4: gsbi@16300000 {
196 compatible = "qcom,gsbi-v1.0.0";
197 cell-index = <4>;
200 clock-names = "iface";
202 #address-cells = <1>;
203 #size-cells = <1>;
206 syscon-tcsr = <&tcsr>;
209 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
214 clock-names = "core", "iface";
219 gsbi5: gsbi@16400000 {
220 compatible = "qcom,gsbi-v1.0.0";
221 cell-index = <5>;
224 clock-names = "iface";
226 #address-cells = <1>;
227 #size-cells = <1>;
230 syscon-tcsr = <&tcsr>;
233 compatible = "qcom,i2c-qup-v1.1.1";
234 #address-cells = <1>;
235 #size-cells = <0>;
240 assigned-clocks = <&gcc GSBI5_QUP_CLK>;
241 assigned-clock-rates = <24000000>;
244 clock-names = "core", "iface";
249 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
254 clock-names = "core", "iface";
262 qcom,controller-type = "pmic-arbiter";
265 sdcc1bam: dma-controller@12182000 {
266 compatible = "qcom,bam-v1.3.0";
270 clock-names = "bam_clk";
271 #dma-cells = <1>;
275 sdcc2bam: dma-controller@12142000 {
276 compatible = "qcom,bam-v1.3.0";
280 clock-names = "bam_clk";
281 #dma-cells = <1>;
288 arm,primecell-periphid = <0x00051180>;
292 clock-names = "mclk", "apb_pclk";
293 bus-width = <8>;
294 max-frequency = <48000000>;
295 cap-sd-highspeed;
296 cap-mmc-highspeed;
297 vmmc-supply = <&vsdcc_fixed>;
299 dma-names = "tx", "rx";
300 assigned-clocks = <&gcc SDC1_CLK>;
301 assigned-clock-rates = <400000>;
306 arm,primecell-periphid = <0x00051180>;
311 clock-names = "mclk", "apb_pclk";
312 bus-width = <4>;
313 cap-sd-highspeed;
314 cap-mmc-highspeed;
315 max-frequency = <48000000>;
316 no-1-8-v;
317 vmmc-supply = <&vsdcc_fixed>;
319 dma-names = "tx", "rx";
320 assigned-clocks = <&gcc SDC2_CLK>;
321 assigned-clock-rates = <400000>;
325 compatible = "qcom,tcsr-mdm9615", "syscon";
330 compatible = "qcom,rpm-mdm9615";
338 interrupt-names = "ack", "err", "wakeup";