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Searched +full:gpu +full:- +full:speedbin (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Dadreno_gpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
35 * @enum adreno_family: identify generation and possibly sub-generation
37 * In some cases there are distinct sub-generations within a major revision
38 * so it helps to be able to group the GPU devices by generation and if
39 * necessary sub-generation.
79 u64 (*get_timestamp)(struct msm_gpu *gpu);
100 uint16_t speedbin; member
108 * @chipids: Table of matching chip-ids
125 * @speedbins: Optional table of fuse to speedbin mappings
147 * Helper to build a speedbin table, ie. the table:
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H A Da6xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
15 #include <linux/soc/qcom/llcc-qcom.h>
19 static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu) in a6xx_gmu_get_timestamp() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_get_timestamp()
27 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H); in a6xx_gmu_get_timestamp()
28 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L); in a6xx_gmu_get_timestamp()
29 temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H); in a6xx_gmu_get_timestamp()
31 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in a6xx_gmu_get_timestamp()
32 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); in a6xx_gmu_get_timestamp()
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H A Da5xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
10 #include <linux/nvmem-consumer.h>
17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
26 if (a5xx_gpu->has_whereami) { in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
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H A Dadreno_gpu.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/nvmem-consumer.h>
26 MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
31 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
34 struct device *dev = &gpu->pdev->dev; in zap_shader_load_mdt()
46 return -EINVAL; in zap_shader_load_mdt()
49 np = of_get_available_child_by_name(dev->of_node, "zap-shader"); in zap_shader_load_mdt()
52 return -ENODEV; in zap_shader_load_mdt()
58 return -EPROBE_DEFER; in zap_shader_load_mdt()
69 * Check for a firmware-name property. This is the new scheme in zap_shader_load_mdt()
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/linux/drivers/nvmem/
H A Dmtk-efuse.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
10 #include <linux/nvmem-provider.h>
26 void __iomem *addr = priv->base + reg; in mtk_reg_read()
50 size_t sz = strlen(cell->name); in mtk_efuse_fixup_dt_cell_info()
53 * On some SoCs, the GPU speedbin is not read as bitmask but as in mtk_efuse_fixup_dt_cell_info()
54 * a number with range [0-7] (max 3 bits): post process to use in mtk_efuse_fixup_dt_cell_info()
55 * it in OPP tables to describe supported-hw. in mtk_efuse_fixup_dt_cell_info()
57 if (cell->nbits <= 3 && in mtk_efuse_fixup_dt_cell_info()
58 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) in mtk_efuse_fixup_dt_cell_info()
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/linux/arch/arm64/boot/dts/qcom/
H A Dsm8650.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/clock/qcom,sm8650-camcc.h>
9 #include <dt-bindings/clock/qcom,sm8650-dispcc.h>
10 #include <dt-bindings/clock/qcom,sm8650-gcc.h>
11 #include <dt-bindings/clock/qcom,sm8650-gpucc.h>
12 #include <dt-bindings/clock/qcom,sm8650-tcsr.h>
13 #include <dt-bindings/clock/qcom,sm8650-videocc.h>
14 #include <dt-bindings/dma/qcom-gpi.h>
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