| /linux/drivers/gpu/drm/msm/adreno/ |
| H A D | a6xx_gpu.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
15 #include <linux/soc/qcom/llcc-qcom.h>
19 static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu) in a6xx_gmu_get_timestamp()
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_get_timestamp()
26 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in a6xx_gmu_get_timestamp()
27 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); in a6xx_gmu_get_timestamp()
28 temp = gmu_read(&a6xx_gpu->gm in a6xx_gmu_get_timestamp()
18 a6xx_gmu_get_timestamp(struct msm_gpu * gpu) a6xx_gmu_get_timestamp() argument
33 fence_status_check(struct msm_gpu * gpu,u32 offset,u32 value,u32 status,u32 mask) fence_status_check() argument
54 struct msm_gpu *gpu = &adreno_gpu->base; fenced_write() local
111 _a6xx_check_idle(struct msm_gpu * gpu) _a6xx_check_idle() argument
129 a6xx_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a6xx_idle() argument
148 update_shadow_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring) update_shadow_rptr() argument
161 a6xx_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a6xx_flush() argument
329 a6xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit) a6xx_submit() argument
453 a7xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit) a7xx_submit() argument
629 a6xx_set_hwcg(struct msm_gpu * gpu,bool state) a6xx_set_hwcg() argument
711 a6xx_set_cp_protect(struct msm_gpu * gpu) a6xx_set_cp_protect() argument
736 a6xx_calc_ubwc_config(struct adreno_gpu * gpu) a6xx_calc_ubwc_config() argument
812 a6xx_set_ubwc_config(struct msm_gpu * gpu) a6xx_set_ubwc_config() argument
874 a7xx_patch_pwrup_reglist(struct msm_gpu * gpu) a7xx_patch_pwrup_reglist() argument
945 a7xx_preempt_start(struct msm_gpu * gpu) a7xx_preempt_start() argument
973 a6xx_cp_init(struct msm_gpu * gpu) a6xx_cp_init() argument
1002 a7xx_cp_init(struct msm_gpu * gpu) a7xx_cp_init() argument
1061 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_ucode_check_version() local
1124 a6xx_ucode_load(struct msm_gpu * gpu) a6xx_ucode_load() argument
1201 a6xx_zap_shader_init(struct msm_gpu * gpu) a6xx_zap_shader_init() argument
1251 hw_init(struct msm_gpu * gpu) hw_init() argument
1619 a6xx_hw_init(struct msm_gpu * gpu) a6xx_hw_init() argument
1632 a6xx_dump(struct msm_gpu * gpu) a6xx_dump() argument
1639 a6xx_recover(struct msm_gpu * gpu) a6xx_recover() argument
1715 a6xx_uche_fault_block(struct msm_gpu * gpu,u32 mid) a6xx_uche_fault_block() argument
1812 a6xx_fault_block(struct msm_gpu * gpu,u32 id) a6xx_fault_block() argument
1832 struct msm_gpu *gpu = arg; a6xx_fault_handler() local
1849 a6xx_cp_hw_err_irq(struct msm_gpu * gpu) a6xx_cp_hw_err_irq() argument
1891 a6xx_fault_detect_irq(struct msm_gpu * gpu) a6xx_fault_detect_irq() argument
1924 a7xx_sw_fuse_violation_irq(struct msm_gpu * gpu) a7xx_sw_fuse_violation_irq() argument
1945 a6xx_gpu_keepalive_vote(struct msm_gpu * gpu,bool on) a6xx_gpu_keepalive_vote() argument
1956 irq_poll_fence(struct msm_gpu * gpu) irq_poll_fence() argument
1978 a6xx_irq(struct msm_gpu * gpu) a6xx_irq() argument
2039 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_llc_activate() local
2099 struct msm_gpu *gpu = &adreno_gpu->base; a7xx_llc_activate() local
2173 struct msm_gpu *gpu = &adreno_gpu->base; a6xx_bus_clear_pending_transactions() local
2208 a6xx_gpu_sw_reset(struct msm_gpu * gpu,bool assert) a6xx_gpu_sw_reset() argument
2224 a6xx_gmu_pm_resume(struct msm_gpu * gpu) a6xx_gmu_pm_resume() argument
2252 a6xx_pm_resume(struct msm_gpu * gpu) a6xx_pm_resume() argument
2311 a6xx_gmu_pm_suspend(struct msm_gpu * gpu) a6xx_gmu_pm_suspend() argument
2338 a6xx_pm_suspend(struct msm_gpu * gpu) a6xx_pm_suspend() argument
2377 a6xx_get_timestamp(struct msm_gpu * gpu) a6xx_get_timestamp() argument
2382 a6xx_active_ring(struct msm_gpu * gpu) a6xx_active_ring() argument
2390 a6xx_destroy(struct msm_gpu * gpu) a6xx_destroy() argument
2419 a6xx_gpu_busy(struct msm_gpu * gpu,unsigned long * out_sample_rate) a6xx_gpu_busy() argument
2435 a6xx_gpu_set_freq(struct msm_gpu * gpu,struct dev_pm_opp * opp,bool suspended) a6xx_gpu_set_freq() argument
2447 a6xx_create_vm(struct msm_gpu * gpu,struct platform_device * pdev) a6xx_create_vm() argument
2465 a6xx_create_private_vm(struct msm_gpu * gpu,bool kernel_managed) a6xx_create_private_vm() argument
2478 a6xx_get_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a6xx_get_rptr() argument
2496 a6xx_progress(struct msm_gpu * gpu,struct msm_ringbuffer * ring) a6xx_progress() argument
2553 a6xx_read_speedbin(struct device * dev,struct a6xx_gpu * a6xx_gpu,const struct adreno_info * info,u32 * speedbin) a6xx_read_speedbin() argument
2575 u32 speedbin; a6xx_set_supported_hw() local
2626 struct msm_gpu *gpu; a6xx_gpu_init() local
2628 u32 speedbin; a6xx_gpu_init() local
[all...] |
| H A D | adreno_gpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/nvmem-consumer.h>
25 MODULE_PARM_DESC(address_space_size, "Override for size of processes private GPU address space");
30 static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, in zap_shader_load_mdt() argument
33 struct device *dev = &gpu->pdev->de in zap_shader_load_mdt()
169 adreno_zap_shader_load(struct msm_gpu * gpu,u32 pasid) adreno_zap_shader_load() argument
188 adreno_create_vm(struct msm_gpu * gpu,struct platform_device * pdev) adreno_create_vm() argument
195 adreno_iommu_create_vm(struct msm_gpu * gpu,struct platform_device * pdev,unsigned long quirks) adreno_iommu_create_vm() argument
229 adreno_private_vm_size(struct msm_gpu * gpu) adreno_private_vm_size() argument
257 struct msm_gpu *gpu = &adreno_gpu->base; adreno_check_and_reenable_stall() local
283 adreno_fault_handler(struct msm_gpu * gpu,unsigned long iova,int flags,struct adreno_smmu_fault_info * info,const char * block,u32 scratch[4]) adreno_fault_handler() argument
359 adreno_get_param(struct msm_gpu * gpu,struct msm_context * ctx,uint32_t param,uint64_t * value,uint32_t * len) adreno_get_param() argument
459 adreno_set_param(struct msm_gpu * gpu,struct msm_context * ctx,uint32_t param,uint64_t value,uint32_t len) adreno_set_param() argument
635 adreno_fw_create_bo(struct msm_gpu * gpu,const struct firmware * fw,u64 * iova) adreno_fw_create_bo() argument
654 adreno_hw_init(struct msm_gpu * gpu) adreno_hw_init() argument
696 struct msm_gpu *gpu = &adreno_gpu->base; get_rptr() local
701 adreno_active_ring(struct msm_gpu * gpu) adreno_active_ring() argument
706 adreno_recover(struct msm_gpu * gpu) adreno_recover() argument
724 adreno_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring,u32 reg) adreno_flush() argument
744 adreno_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring) adreno_idle() argument
760 adreno_gpu_state_get(struct msm_gpu * gpu,struct msm_gpu_state * state) adreno_gpu_state_get() argument
938 adreno_show(struct msm_gpu * gpu,struct msm_gpu_state * state,struct drm_printer * p) adreno_show() argument
1036 adreno_dump_info(struct msm_gpu * gpu) adreno_dump_info() argument
1058 adreno_dump(struct msm_gpu * gpu) adreno_dump() argument
1099 adreno_get_pwrlevels(struct device * dev,struct msm_gpu * gpu) adreno_get_pwrlevels() argument
1181 adreno_read_speedbin(struct device * dev,u32 * speedbin) adreno_read_speedbin() argument
1193 struct msm_gpu *gpu = &adreno_gpu->base; adreno_gpu_init() local
1249 struct msm_gpu *gpu = &adreno_gpu->base; adreno_gpu_cleanup() local
[all...] |
| /linux/drivers/nvmem/ |
| H A D | mtk-efuse.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
11 #include <linux/nvmem-provider.h>
27 void __iomem *addr = priv->base + reg; in mtk_reg_read()
51 size_t sz = strlen(cell->name); in mtk_efuse_fixup_dt_cell_info()
54 * On some SoCs, the GPU speedbin is not read as bitmask but as in mtk_efuse_fixup_dt_cell_info()
55 * a number with range [0-7] (max 3 bits): post process to use in mtk_efuse_fixup_dt_cell_info()
56 * it in OPP tables to describe supported-hw. in mtk_efuse_fixup_dt_cell_info()
58 if (cell->nbits <= 3 && in mtk_efuse_fixup_dt_cell_info()
59 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) in mtk_efuse_fixup_dt_cell_info()
[all …]
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