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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu_v2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Etnaviv Project
7 #include <linux/dma-mapping.h>
32 unsigned short id; member
52 drm_mm_takedown(&context->mm); in etnaviv_iommuv2_free()
55 if (v2_context->stlb_cpu[i]) in etnaviv_iommuv2_free()
56 dma_free_wc(context->global->dev, SZ_4K, in etnaviv_iommuv2_free()
57 v2_context->stlb_cpu[i], in etnaviv_iommuv2_free()
58 v2_context->stlb_dma[i]); in etnaviv_iommuv2_free()
61 dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu, in etnaviv_iommuv2_free()
[all …]
H A Detnaviv_drv.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2015-2018 Etnaviv Project
32 int id; member
39 struct etnaviv_gpu *gpu[ETNA_MAX_PIPES]; member
72 u16 etnaviv_buffer_init(struct etnaviv_gpu *gpu);
73 u16 etnaviv_buffer_config_mmuv2(struct etnaviv_gpu *gpu, u32 mtlb_addr, u32 safe_addr);
74 u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id);
75 void etnaviv_buffer_end(struct etnaviv_gpu *gpu);
76 void etnaviv_sync_point_queue(struct etnaviv_gpu *gpu, unsigned int event);
77 void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state,
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H A Detnaviv_drv.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2018 Etnaviv Project
7 #include <linux/dma-mapping.h>
46 struct etnaviv_drm_private *priv = dev->dev_private; in load_gpu()
50 struct etnaviv_gpu *g = priv->gpu[i]; in load_gpu()
57 priv->gpu[i] = NULL; in load_gpu()
64 struct etnaviv_drm_private *priv = dev->dev_private; in etnaviv_open()
70 return -ENOMEM; in etnaviv_open()
72 ret = xa_alloc_cyclic(&priv->active_contexts, &ctx->id, ctx, in etnaviv_open()
73 xa_limit_32b, &priv->next_context_id, GFP_KERNEL); in etnaviv_open()
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/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_preempt.c1 // SPDX-License-Identifier: GPL-2.0-only
15 enum preempt_state cur = atomic_cmpxchg(&a5xx_gpu->preempt_state, in try_preempt_state()
25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
48 spin_lock_irqsave(&ring->preempt_lock, flags); in update_wptr()
50 spin_unlock_irqrestore(&ring->preempt_lock, flags); in update_wptr()
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
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H A Da5xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
10 #include <linux/nvmem-consumer.h>
17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
26 if (a5xx_gpu->has_whereami) { in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
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H A Da6xx_gpu_state.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
110 list_add_tail(&obj->node, &a6xx_state->objs); in state_kcalloc()
111 return &obj->data; in state_kcalloc()
125 * Allocate 1MB for the crashdumper scratch region - 8k for the script and
129 #define A6XX_CD_DATA_SIZE (SZ_1M - 8192)
131 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
134 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
135 SZ_1M, MSM_BO_WC, gpu->vm, in a6xx_crashdumper_init()
136 &dumper->bo, &dumper->iova); in a6xx_crashdumper_init()
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H A Da5xx_gpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
54 void a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor);
61 * PREEMPT_NONE - no preemption in progress. Next state START.
62 * PREEMPT_START - The trigger is evaulating if preemption is possible. Next
64 * PREEMPT_ABORT - An intermediate state before moving back to NONE. Next
70 * PREEMPT_PENDING: Preemption complete interrupt fired - the callback is
98 * @info: Type of the record - written 0 by the CPU, updated by the CP
106 * @counter: GPU address of the storage area for the performance counters
137 int a5xx_power_init(struct msm_gpu *gpu);
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/linux/drivers/gpu/vga/
H A Dvga_switcheroo.c2 * vga_switcheroo.c - Support for laptop with dual GPU using one set of outputs
33 #include <linux/apple-gmux.h>
66 * for the inactive GPU.) Also, muxes are often used to cut power to the
67 * discrete GPU while it is not used.
71 * handler to control the power state of the discrete GPU, its ->switchto
72 * callback is a no-op for obvious reasons. The discrete GPU is often equipped
75 * suspend/resume order when changing the discrete GPU's power state. In total
77 * client (on the discrete GPU). The code is mostly prepared to support
80 * The GPU to which the outputs are currently switched is called the
81 * active client in vga_switcheroo parlance. The GPU not in use is the
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_atpx_handler.c1 // SPDX-License-Identifier: GPL-2.0-only
37 /* handle for device - and atpx */
85 * radeon_atpx_call - call an ATPX method
110 atpx_arg_elements[1].buffer.length = params->length; in radeon_atpx_call()
111 atpx_arg_elements[1].buffer.pointer = params->pointer; in radeon_atpx_call()
132 * radeon_atpx_parse_functions - parse supported functions
143 f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED; in radeon_atpx_parse_functions()
144 f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
145 f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
146 f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
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/linux/sound/hda/codecs/hdmi/
H A Dnvhdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
23 * - 0x10de0015
24 * - 0x10de0040
29 if (cap->ca_index == 0x00 && channels == 2) in nvhdmi_chmap_cea_alloc_validate_get_type()
33 if (cap->channels != channels) in nvhdmi_chmap_cea_alloc_validate_get_type()
34 return -1; in nvhdmi_chmap_cea_alloc_validate_get_type()
44 return -EINVAL; in nvhdmi_chmap_validate()
49 /* map from pin NID to port; port is 0-based */
53 return pin_nid - 4; in nvhdmi_pin2port()
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/linux/include/uapi/drm/
H A Damdgpu_drm.h1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
86 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
89 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
90 * GPU'
1252 __u32 id; global() member
[all...]
H A Dlima_drm.h1 /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
2 /* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
27 * get various information of the GPU
43 * create a buffer for used by GPU
57 __u32 va; /* out, virtual address mapped into GPU MMU */
67 __u32 flags; /* in, buffer read/write by GPU */
80 /* frame used to setup mali400 GPU PP for each task */
89 /* frame used to setup mali450 GPU PP for each task */
109 * submit a task to GPU
132 * wait pending GPU task finish of a buffer
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H A Dpanthor_drm.h1 /* SPDX-License-Identifier: MIT */
19 * - Structures must be aligned on 64-bit/8-byte. If the object is not
21 * - Fields must be explicitly aligned to their natural type alignment with
23 * - All padding fields will be checked by the driver to make sure they are
25 * - Flags can be added, but not removed/replaced.
26 * - New fields can be added to the main structures (the structures
31 * - Ne
460 __u32 id; global() member
490 __u32 id; global() member
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/linux/Documentation/gpu/
H A Dmsm-crash-dump.rst7 Following a GPU hang the MSM driver outputs debugging information via
14 by a (-).
17 --------
35 ID of the GPU that generated the crash formatted as
38 rbbm-status
39 The current value of RBBM_STATUS which shows what top level GPU
44 identified with an id number.
46 id
47 Ringbuffer ID (0 based index). Each ringbuffer in the section
48 will have its own unique id.
[all …]
/linux/include/linux/
H A Dvga_switcheroo.h2 * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs
39 * enum vga_switcheroo_handler_flags_t - handler flags bitmask
45 * GPU needs to train the link and communicate the link parameters to the
46 * inactive GPU (mediated by vga_switcheroo). The inactive GPU may then
47 * skip the AUX handshake and set up its output with these pre-calibrated
59 * enum vga_switcheroo_state - client power state
76 * enum vga_switcheroo_client_id - client identifier
78 * Determining the id requires the handler, so GPUs are given their
79 * true id in a delayed fashion in vga_switcheroo_enable()
94 * struct vga_switcheroo_handler - handler callbacks
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/linux/drivers/power/sequencing/
H A Dpwrseq-thead-gpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * T-HEAD TH1520 GPU Power Sequencer Driver
8 * This driver implements the power sequence for the Imagination BXM-4-64
9 * GPU on the T-HEAD TH1520 SoC. The sequence requires coordinating resources
10 * from both the sequencer's parent device node (clkgen_reset) and the GPU's
13 * The `match` function is used to acquire the GPU's resources when the
14 * GPU driver requests the "gpu-power" sequence target.
26 #include <dt-bindings/power/thead,th1520-power.h>
45 if (!ctx->clks || !ctx->gpu_reset) in pwrseq_thead_gpu_enable()
46 return -ENODEV; in pwrseq_thead_gpu_enable()
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/linux/drivers/platform/x86/
H A Dapple-gmux.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2012 Andreas Heider <andreas@meetr.de>
19 #include <linux/apple-gmux.h>
32 * A `Lattice XP2`_ on pre-retinas, a `Renesas R4F2113`_ on pre-T2 retinas.
36 * the voltage regulators of the discrete GPU, drives the display panel power,
41 * dual GPUs but no built-in display.)
45 * to access a pre-retina gmux are infixed ``_pio_``, those for a pre-T2
54 * https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf
112 return inb(gmux_data->iostart + port); in gmux_pio_read8()
118 outb(val, gmux_data->iostart + port); in gmux_pio_write8()
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/linux/Documentation/devicetree/bindings/gpu/
H A Dimg,powervr-sgx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 # Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
5 ---
6 $id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Frank Binns <frank.binns@imgtec.com>
17 - items:
18 - enum:
19 - ti,omap3430-gpu # Rev 121
20 - ti,omap3630-gpu # Rev 125
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H A Dvivante,gc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Vivante GPU
9 description: Vivante GPU core devices
12 - Lucas Stach <l.stach@pengutronix.de>
24 '#cooling-cells':
27 assigned-clock-parents: true
28 assigned-clock-rates: true
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H A Darm,mali-valhall-csf.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-valhall-csf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Mali Valhall GPU
10 - Liviu Dudau <liviu.dudau@arm.com>
11 - Boris Brezillon <boris.brezillon@collabora.com>
15 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - enum:
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
[all …]
/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_gpu.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-mapping.h>
27 if (test_bit(PANFROST_COMP_BIT_GPU, pfdev->is_suspended)) in panfrost_gpu_irq_handler()
39 dev_warn(pfdev->dev, "GPU Fault 0x%08x (%s) at 0x%016llx\n", in panfrost_gpu_irq_handler()
44 dev_warn(pfdev->dev, "There were multiple GPU faults - some have not been reported\n"); in panfrost_gpu_irq_handler()
68 clear_bit(PANFROST_COMP_BIT_GPU, pfdev->is_suspended); in panfrost_gpu_soft_reset()
71 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, in panfrost_gpu_soft_reset()
75 dev_err(pfdev->dev, "gpu soft reset timed out, attempting hard reset\n"); in panfrost_gpu_soft_reset()
78 ret = readl_relaxed_poll_timeout(pfdev->iomem + GPU_INT_RAWSTAT, val, in panfrost_gpu_soft_reset()
81 dev_err(pfdev->dev, "gpu hard reset timed out\n"); in panfrost_gpu_soft_reset()
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_topology.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
46 /* topology_device_list - Master list of all topology devices */
60 if (top_dev->proximity_domain == proximity_domain) { in kfd_topology_device_by_proximity_domain_no_lock()
90 if (top_dev->gpu_id == gpu_id) { in kfd_topology_device_by_id()
108 return top_dev->gpu; in kfd_device_by_id()
120 list_del(&dev->list); in kfd_release_topology_device()
122 while (dev->mem_props.next != &dev->mem_props) { in kfd_release_topology_device()
123 mem = container_of(dev->mem_props.next, in kfd_release_topology_device()
125 list_del(&mem->list); in kfd_release_topology_device()
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/linux/Documentation/gpu/rfc/
H A Di915_vm_bind.h1 /* SPDX-License-Identifier: MIT */
32 * Flag to opt-in for VM_BIND mode of binding during VM creation.
51 * struct drm_i915_gem_timeline_fence - An input or output timeline fence.
74 #define __I915_TIMELINE_FENCE_UNKNOWN_FLAGS (-(I915_TIMELINE_FENCE_SIGNAL << 1))
86 * struct drm_i915_gem_vm_bind - VA to object mapping to bind.
88 * This structure is passed to VM_BIND ioctl and specifies the mapping of GPU
98 * platform, for binding device local-memory objects, the @start, @offset and
102 * Error code -EINVAL will be returned if @start, @offset and @length are not
104 * -ENOSPC will be returned if the VA range specified can't be reserved.
111 /** @vm_id: VM (address space) id to bind */
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/linux/include/uapi/linux/
H A Dkfd_ioctl.h30 * - 1.1 - initial version
31 * - 1.3 - Add SMI events support
32 * - 1.4 - Indicate new SRAM EDC bit in device properties
33 * - 1.5 - Add SVM API
34 * - 1.6 - Query clear flags in SVM get_attr API
35 * - 1.7 - Checkpoint Restore (CRIU) API
36 * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs
37 * - 1.9 - Add available memory ioctl
38 * - 1.10 - Add SMI profiler event log
39 * - 1.11 - Add unified memory for ctx save/restore area
[all …]

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