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/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_preempt.c1 // SPDX-License-Identifier: GPL-2.0
19 enum a6xx_preempt_state cur = atomic_cmpxchg(&a6xx_gpu->preempt_state, in try_preempt_state()
29 static inline void set_preempt_state(struct a6xx_gpu *gpu, in set_preempt_state() argument
38 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
49 spin_lock_irqsave(&ring->preempt_lock, flags); in update_wptr()
51 if (ring->restore_wptr) { in update_wptr()
56 ring->restore_wptr = false; in update_wptr()
59 spin_unlock_irqrestore(&ring->preempt_lock, flags); in update_wptr()
63 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
65 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
[all …]
H A Da5xx_preempt.c1 // SPDX-License-Identifier: GPL-2.0-only
15 enum preempt_state cur = atomic_cmpxchg(&a5xx_gpu->preempt_state, in try_preempt_state()
25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
48 spin_lock_irqsave(&ring->preempt_lock, flags); in update_wptr()
50 spin_unlock_irqrestore(&ring->preempt_lock, flags); in update_wptr()
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
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H A Da6xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
15 #include <linux/soc/qcom/llcc-qcom.h>
24 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in read_gmu_ao_counter()
25 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); in read_gmu_ao_counter()
26 temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in read_gmu_ao_counter()
32 static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) in fence_status_check() argument
41 gpu_write(gpu, offset, value); in fence_status_check()
52 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in fenced_write()
53 struct msm_gpu *gpu = &adreno_gpu->base; in fenced_write() local
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H A Da8xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/soc/qcom/llcc-qcom.h>
19 static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) in a8xx_aperture_slice_set() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_slice_set()
27 if (a6xx_gpu->cached_aperture == val) in a8xx_aperture_slice_set()
30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); in a8xx_aperture_slice_set()
32 a6xx_gpu->cached_aperture = val; in a8xx_aperture_slice_set()
35 static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) in a8xx_aperture_acquire() argument
37 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_acquire()
40 spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); in a8xx_aperture_acquire()
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H A Da5xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
10 #include <linux/nvmem-consumer.h>
17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
26 if (a5xx_gpu->has_whereami) { in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
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H A Da6xx_gpu_state.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
110 list_add_tail(&obj->node, &a6xx_state->objs); in state_kcalloc()
111 return &obj->data; in state_kcalloc()
125 * Allocate 1MB for the crashdumper scratch region - 8k for the script and
129 #define A6XX_CD_DATA_SIZE (SZ_1M - 8192)
131 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
134 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
135 SZ_1M, MSM_BO_WC, gpu->vm, in a6xx_crashdumper_init()
136 &dumper->bo, &dumper->iova); in a6xx_crashdumper_init()
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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu_v2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Etnaviv Project
7 #include <linux/dma-mapping.h>
32 unsigned short id; member
52 drm_mm_takedown(&context->mm); in etnaviv_iommuv2_free()
55 if (v2_context->stlb_cpu[i]) in etnaviv_iommuv2_free()
56 dma_free_wc(context->global->dev, SZ_4K, in etnaviv_iommuv2_free()
57 v2_context->stlb_cpu[i], in etnaviv_iommuv2_free()
58 v2_context->stlb_dma[i]); in etnaviv_iommuv2_free()
61 dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu, in etnaviv_iommuv2_free()
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/linux/drivers/gpu/drm/msm/
H A Dmsm_ringbuffer.c1 // SPDX-License-Identifier: GPL-2.0-only
17 struct msm_fence_context *fctx = submit->ring->fctx; in msm_job_run()
18 struct msm_gpu *gpu = submit->gpu; in msm_job_run() local
19 struct msm_drm_private *priv = gpu->dev->dev_private; in msm_job_run()
20 unsigned nr_cmds = submit->nr_cmds; in msm_job_run()
23 msm_fence_init(submit->hw_fence, fctx); in msm_job_run()
25 mutex_lock(&priv->lru.lock); in msm_job_run()
27 for (i = 0; i < submit->nr_bos; i++) { in msm_job_run()
28 struct drm_gem_object *obj = submit->bos[i].obj; in msm_job_run()
33 submit->bos_pinned = false; in msm_job_run()
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H A Dmsm_submitqueue.c1 // SPDX-License-Identifier: GPL-2.0-only
10 int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sysprof) in msm_context_set_sysprof() argument
20 return UERR(EINVAL, gpu->dev, "Invalid sysprof: %d", sysprof); in msm_context_set_sysprof()
22 pm_runtime_get_sync(&gpu->pdev->dev); in msm_context_set_sysprof()
25 refcount_inc(&gpu->sysprof_active); in msm_context_set_sysprof()
32 switch (ctx->sysprof) { in msm_context_set_sysprof()
34 pm_runtime_put_autosuspend(&gpu->pdev->dev); in msm_context_set_sysprof()
37 refcount_dec(&gpu->sysprof_active); in msm_context_set_sysprof()
43 /* Some gpu families require additional setup for sysprof */ in msm_context_set_sysprof()
44 if (gpu->funcs->sysprof_setup) in msm_context_set_sysprof()
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H A Dmsm_gpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/adreno-smmu-priv.h>
49 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
51 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
53 int (*hw_init)(struct msm_gpu *gpu);
58 int (*ucode_load)(struct msm_gpu *gpu);
60 int (*pm_suspend)(struct msm_gpu *gpu);
61 int (*pm_resume)(struct msm_gpu *gpu);
62 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
63 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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/linux/drivers/gpu/vga/
H A Dvga_switcheroo.c2 * vga_switcheroo.c - Support for laptop with dual GPU using one set of outputs
33 #include <linux/apple-gmux.h>
66 * for the inactive GPU.) Also, muxes are often used to cut power to the
67 * discrete GPU while it is not used.
71 * handler to control the power state of the discrete GPU, its ->switchto
72 * callback is a no-op for obvious reasons. The discrete GPU is often equipped
75 * suspend/resume order when changing the discrete GPU's power state. In total
77 * client (on the discrete GPU). The code is mostly prepared to support
80 * The GPU to which the outputs are currently switched is called the
81 * active client in vga_switcheroo parlance. The GPU not in use is the
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/linux/drivers/gpu/drm/radeon/
H A Dradeon_atpx_handler.c1 // SPDX-License-Identifier: GPL-2.0-only
37 /* handle for device - and atpx */
85 * radeon_atpx_call - call an ATPX method
110 atpx_arg_elements[1].buffer.length = params->length; in radeon_atpx_call()
111 atpx_arg_elements[1].buffer.pointer = params->pointer; in radeon_atpx_call()
132 * radeon_atpx_parse_functions - parse supported functions
143 f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED; in radeon_atpx_parse_functions()
144 f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
145 f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
146 f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
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/linux/sound/hda/codecs/hdmi/
H A Dnvhdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
23 * - 0x10de0015
24 * - 0x10de0040
29 if (cap->ca_index == 0x00 && channels == 2) in nvhdmi_chmap_cea_alloc_validate_get_type()
33 if (cap->channels != channels) in nvhdmi_chmap_cea_alloc_validate_get_type()
34 return -1; in nvhdmi_chmap_cea_alloc_validate_get_type()
44 return -EINVAL; in nvhdmi_chmap_validate()
49 /* map from pin NID to port; port is 0-based */
53 return pin_nid - 4; in nvhdmi_pin2port()
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/linux/drivers/gpu/drm/i915/gvt/
H A Dvgpu.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
45 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in populate_pvinfo_page()
51 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; in populate_pvinfo_page()
71 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); in populate_pvinfo_page()
78 drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE); in populate_pvinfo_page()
82 * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU
87 * vGPU on same physical GPU depending on available resource. Each vGPU
103 * intel_gvt_init_vgpu_types - initialize vGPU type list
111 unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; in intel_gvt_init_vgpu_types()
112 unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; in intel_gvt_init_vgpu_types()
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/linux/include/uapi/drm/
H A Damdgpu_drm.h1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
86 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
89 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
90 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
91 * pages of system memory, allows GPU access system memory in a linearized
97 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
161 * May depend on GPU instructions to flush caches to system scope explicitly.
167 /* Flag that BO should not be cached by GPU. Coherent without having to flush
168 * GPU caches explicitly
174 /* Flag that BO should be coherent across devices when using device-level
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/linux/Documentation/gpu/
H A Dmsm-crash-dump.rst7 Following a GPU hang the MSM driver outputs debugging information via
14 by a (-).
17 --------
35 ID of the GPU that generated the crash formatted as
38 rbbm-status
39 The current value of RBBM_STATUS which shows what top level GPU
44 identified with an id number.
46 id
47 Ringbuffer ID (0 based index). Each ringbuffer in the section
48 will have its own unique id.
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/linux/include/linux/
H A Dvga_switcheroo.h2 * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs
39 * enum vga_switcheroo_handler_flags_t - handler flags bitmask
45 * GPU needs to train the link and communicate the link parameters to the
46 * inactive GPU (mediated by vga_switcheroo). The inactive GPU may then
47 * skip the AUX handshake and set up its output with these pre-calibrated
59 * enum vga_switcheroo_state - client power state
76 * enum vga_switcheroo_client_id - client identifier
78 * Determining the id requires the handler, so GPUs are given their
79 * true id in a delayed fashion in vga_switcheroo_enable()
94 * struct vga_switcheroo_handler - handler callbacks
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_device.c1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
20 #include <linux/dma-mapping.h>
40 * pvr_device_reg_init() - Initialize kernel access to a PowerVR device's
44 * Sets struct pvr_device->regs.
58 struct platform_device *plat_dev = to_platform_device(drm_dev->dev); in pvr_device_reg_init()
62 pvr_dev->regs_resource = NULL; in pvr_device_reg_init()
63 pvr_dev->regs = NULL; in pvr_device_reg_init()
67 return dev_err_probe(drm_dev->dev, PTR_ERR(regs), in pvr_device_reg_init()
68 "failed to ioremap gpu registers\n"); in pvr_device_reg_init()
70 pvr_dev->regs = regs; in pvr_device_reg_init()
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_topology.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
46 /* topology_device_list - Master list of all topology devices */
60 if (top_dev->proximity_domain == proximity_domain) { in kfd_topology_device_by_proximity_domain_no_lock()
90 if (top_dev->gpu_id == gpu_id) { in kfd_topology_device_by_id()
108 return top_dev->gpu; in kfd_device_by_id()
120 list_del(&dev->list); in kfd_release_topology_device()
122 while (dev->mem_props.next != &dev->mem_props) { in kfd_release_topology_device()
123 mem = container_of(dev->mem_props.next, in kfd_release_topology_device()
125 list_del(&mem->list); in kfd_release_topology_device()
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H A Dkfd_crat.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2015-2022 Advanced Micro Devices, Inc.
33 /* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
34 * GPU processor ID are expressed with Bit[31]=1.
35 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
40 /* Return the next available gpu_processor_id and increment it for next GPU
41 * @total_cu_count - Total CUs present in the GPU including ones
172 /* L2 Data Cache per GPU (Total Tex Cache) */
215 /* L2 Data Cache per GPU (Total Tex Cache) */
258 /* L2 Data Cache per GPU (Total Tex Cache) */
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/linux/drivers/platform/x86/
H A Dapple-gmux.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2010-2012 Andreas Heider <andreas@meetr.de>
19 #include <linux/apple-gmux.h>
32 * A `Lattice XP2`_ on pre-retinas, a `Renesas R4F2113`_ on pre-T2 retinas.
36 * the voltage regulators of the discrete GPU, drives the display panel power,
41 * dual GPUs but no built-in display.)
45 * to access a pre-retina gmux are infixed ``_pio_``, those for a pre-T2
54 * https://www.nxp.com/docs/en/data-sheet/PCAL6524.pdf
112 return inb(gmux_data->iostart + port); in gmux_pio_read8()
118 outb(val, gmux_data->iostart + port); in gmux_pio_write8()
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/linux/drivers/power/sequencing/
H A Dpwrseq-thead-gpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * T-HEAD TH1520 GPU Power Sequencer Driver
8 * This driver implements the power sequence for the Imagination BXM-4-64
9 * GPU on the T-HEAD TH1520 SoC. The sequence requires coordinating resources
10 * from both the sequencer's parent device node (clkgen_reset) and the GPU's
13 * The `match` function is used to acquire the GPU's resources when the
14 * GPU driver requests the "gpu-power" sequence target.
26 #include <dt-bindings/power/thead,th1520-power.h>
45 if (!ctx->clks || !ctx->gpu_reset) in pwrseq_thead_gpu_enable()
46 return -ENODEV; in pwrseq_thead_gpu_enable()
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/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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/linux/Documentation/devicetree/bindings/gpu/
H A Dimg,powervr-sgx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 # Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
5 ---
6 $id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
7 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Frank Binns <frank.binns@imgtec.com>
17 - items:
18 - enum:
19 - ti,omap3430-gpu # Rev 121
20 - ti,omap3630-gpu # Rev 125
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H A Dimg,powervr-rogue.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Frank Binns <frank.binns@imgtec.com>
16 - items:
17 - enum:
18 - renesas,r8a7796-gpu
19 - renesas,r8a77961-gpu
20 - const: img,img-gx6250
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