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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_iommu_v2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Etnaviv Project
7 #include <linux/dma-mapping.h>
32 unsigned short id; member
52 drm_mm_takedown(&context->mm); in etnaviv_iommuv2_free()
55 if (v2_context->stlb_cpu[i]) in etnaviv_iommuv2_free()
56 dma_free_wc(context->global->dev, SZ_4K, in etnaviv_iommuv2_free()
57 v2_context->stlb_cpu[i], in etnaviv_iommuv2_free()
58 v2_context->stlb_dma[i]); in etnaviv_iommuv2_free()
61 dma_free_wc(context->global->dev, SZ_4K, v2_context->mtlb_cpu, in etnaviv_iommuv2_free()
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da5xx_preempt.c1 // SPDX-License-Identifier: GPL-2.0-only
15 enum preempt_state cur = atomic_cmpxchg(&a5xx_gpu->preempt_state, in try_preempt_state()
25 static inline void set_preempt_state(struct a5xx_gpu *gpu, in set_preempt_state() argument
34 atomic_set(&gpu->preempt_state, new); in set_preempt_state()
40 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_wptr() argument
48 spin_lock_irqsave(&ring->preempt_lock, flags); in update_wptr()
50 spin_unlock_irqrestore(&ring->preempt_lock, flags); in update_wptr()
52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
56 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu) in get_next_ring() argument
58 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in get_next_ring()
[all …]
H A Da8xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/soc/qcom/llcc-qcom.h>
19 static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) in a8xx_aperture_slice_set() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_slice_set()
27 if (a6xx_gpu->cached_aperture == val) in a8xx_aperture_slice_set()
30 gpu_write(gpu, REG_A8XX_CP_APERTURE_CNTL_HOST, val); in a8xx_aperture_slice_set()
32 a6xx_gpu->cached_aperture = val; in a8xx_aperture_slice_set()
35 static void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) in a8xx_aperture_acquire() argument
37 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a8xx_aperture_acquire()
40 spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); in a8xx_aperture_acquire()
[all …]
H A Da6xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
15 #include <linux/soc/qcom/llcc-qcom.h>
19 static u64 a6xx_gmu_get_timestamp(struct msm_gpu *gpu) in a6xx_gmu_get_timestamp() argument
21 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a6xx_gmu_get_timestamp()
27 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H); in a6xx_gmu_get_timestamp()
28 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_L); in a6xx_gmu_get_timestamp()
29 temp = gmu_read(&a6xx_gpu->gmu, REG_A7XX_GMU_CX_AO_COUNTER_H); in a6xx_gmu_get_timestamp()
31 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in a6xx_gmu_get_timestamp()
32 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); in a6xx_gmu_get_timestamp()
[all …]
H A Da5xx_gpu.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
10 #include <linux/nvmem-consumer.h>
17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in update_shadow_rptr() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in update_shadow_rptr()
26 if (a5xx_gpu->has_whereami) { in update_shadow_rptr()
33 void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, in a5xx_flush() argument
36 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
46 update_shadow_rptr(gpu, ring); in a5xx_flush()
[all …]
H A Da6xx_gpu_state.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */
112 list_add_tail(&obj->node, &a6xx_state->objs); in state_kcalloc()
113 return &obj->data; in state_kcalloc()
127 * Allocate 1MB for the crashdumper scratch region - 8k for the script and
131 #define A6XX_CD_DATA_SIZE (SZ_1M - 8192)
133 static int a6xx_crashdumper_init(struct msm_gpu *gpu, in a6xx_crashdumper_init() argument
136 dumper->ptr = msm_gem_kernel_new(gpu->dev, in a6xx_crashdumper_init()
137 SZ_1M, MSM_BO_WC, gpu->vm, in a6xx_crashdumper_init()
138 &dumper->bo, &dumper->iova); in a6xx_crashdumper_init()
[all …]
/linux/drivers/gpu/drm/msm/
H A Dmsm_ringbuffer.c1 // SPDX-License-Identifier: GPL-2.0-only
17 struct msm_fence_context *fctx = submit->ring->fctx; in msm_job_run()
18 struct msm_gpu *gpu = submit->gpu; in msm_job_run() local
19 struct drm_device *dev = gpu->dev; in msm_job_run()
20 unsigned nr_cmds = submit->nr_cmds; in msm_job_run()
23 msm_fence_init(submit->hw_fence, fctx); in msm_job_run()
25 mutex_lock(&dev->gem_lru_mutex); in msm_job_run()
27 for (i = 0; i < submit->nr_bos; i++) { in msm_job_run()
28 struct drm_gem_object *obj = submit->bos[i].obj; in msm_job_run()
33 submit->bos_pinned = false; in msm_job_run()
[all …]
H A Dmsm_submitqueue.c1 // SPDX-License-Identifier: GPL-2.0-only
10 int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sysprof) in msm_context_set_sysprof() argument
12 guard(rwsem_write)(&ctx->ctxlock); in msm_context_set_sysprof()
22 return UERR(EINVAL, gpu->dev, "Invalid sysprof: %d", sysprof); in msm_context_set_sysprof()
24 pm_runtime_get_sync(&gpu->pdev->dev); in msm_context_set_sysprof()
27 refcount_inc(&gpu->sysprof_active); in msm_context_set_sysprof()
34 switch (ctx->sysprof) { in msm_context_set_sysprof()
36 pm_runtime_put_autosuspend(&gpu->pdev->dev); in msm_context_set_sysprof()
39 refcount_dec(&gpu->sysprof_active); in msm_context_set_sysprof()
45 /* Some gpu families require additional setup for sysprof */ in msm_context_set_sysprof()
[all …]
H A Dmsm_gpu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/adreno-smmu-priv.h>
50 int (*get_param)(struct msm_gpu *gpu, struct msm_context *ctx,
52 int (*set_param)(struct msm_gpu *gpu, struct msm_context *ctx,
54 int (*hw_init)(struct msm_gpu *gpu);
59 int (*ucode_load)(struct msm_gpu *gpu);
61 int (*pm_suspend)(struct msm_gpu *gpu);
62 int (*pm_resume)(struct msm_gpu *gpu);
63 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit);
64 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
[all …]
H A Dmsm_ringbuffer.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 ((ring)->memptrs_iova + offsetof(struct msm_rbmemptrs, member))
50 struct msm_gpu *gpu; member
51 int id; member
63 * List of in-flight submits on this ring. Protected by submit_lock.
68 * hangcheck detection and keep track of submit jobs that are in-
84 * due to it appearing that the GPU is making forward progress.
86 * For GPU generations which support progress detection (see.
87 * msm_gpu_funcs::progress()), if the GPU appears to be making progress
99 * last_cp_state: The state of the CP at the last call to gpu->progress()
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_atpx_handler.c1 // SPDX-License-Identifier: GPL-2.0-only
37 /* handle for device - and atpx */
85 * radeon_atpx_call - call an ATPX method
110 atpx_arg_elements[1].buffer.length = params->length; in radeon_atpx_call()
111 atpx_arg_elements[1].buffer.pointer = params->pointer; in radeon_atpx_call()
132 * radeon_atpx_parse_functions - parse supported functions
143 f->px_params = mask & ATPX_GET_PX_PARAMETERS_SUPPORTED; in radeon_atpx_parse_functions()
144 f->power_cntl = mask & ATPX_POWER_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
145 f->disp_mux_cntl = mask & ATPX_DISPLAY_MUX_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
146 f->i2c_mux_cntl = mask & ATPX_I2C_MUX_CONTROL_SUPPORTED; in radeon_atpx_parse_functions()
[all …]
/linux/sound/hda/codecs/hdmi/
H A Dnvhdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
23 * - 0x10de0015
24 * - 0x10de0040
29 if (cap->ca_index == 0x00 && channels == 2) in nvhdmi_chmap_cea_alloc_validate_get_type()
33 if (cap->channels != channels) in nvhdmi_chmap_cea_alloc_validate_get_type()
34 return -1; in nvhdmi_chmap_cea_alloc_validate_get_type()
44 return -EINVAL; in nvhdmi_chmap_validate()
49 /* map from pin NID to port; port is 0-based */
53 return pin_nid - 4; in nvhdmi_pin2port()
[all …]
/linux/drivers/gpu/drm/i915/gvt/
H A Dvgpu.c2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
45 struct drm_i915_private *i915 = vgpu->gvt->gt->i915; in populate_pvinfo_page()
51 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id; in populate_pvinfo_page()
71 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id); in populate_pvinfo_page()
78 drm_WARN_ON(&i915->drm, sizeof(struct vgt_if) != VGT_PVINFO_SIZE); in populate_pvinfo_page()
82 * vGPU type name is defined as GVTg_Vx_y which contains the physical GPU
87 * vGPU on same physical GPU depending on available resource. Each vGPU
103 * intel_gvt_init_vgpu_types - initialize vGPU type list
111 unsigned int low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE; in intel_gvt_init_vgpu_types()
112 unsigned int high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE; in intel_gvt_init_vgpu_types()
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/display/msm/gpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
14 # as a work-around:
20 - qcom,adreno
21 - amd,imageon
23 - compatible
28 - description: |
[all …]
/linux/include/uapi/drm/
H A Damdgpu_drm.h1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
88 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
91 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
92 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
93 * pages of system memory, allows GPU access system memory in a linearized
99 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
163 * May depend on GPU instructions to flush caches to system scope explicitly.
169 /* Flag that BO should not be cached by GPU. Coherent without having to flush
170 * GPU caches explicitly
176 /* Flag that BO should be coherent across devices when using device-level
[all …]
H A Dlima_drm.h1 /* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR MIT */
2 /* Copyright 2017-2018 Qiang Yu <yuq825@gmail.com> */
27 * get various information of the GPU
43 * create a buffer for used by GPU
57 __u32 va; /* out, virtual address mapped into GPU MMU */
67 __u32 flags; /* in, buffer read/write by GPU */
80 /* frame used to setup mali400 GPU PP for each task */
89 /* frame used to setup mali450 GPU PP for each task */
109 * submit a task to GPU
132 * wait pending GPU task finish of a buffer
[all …]
/linux/Documentation/gpu/
H A Dmsm-crash-dump.rst7 Following a GPU hang the MSM driver outputs debugging information via
14 by a (-).
17 --------
35 ID of the GPU that generated the crash formatted as
38 rbbm-status
39 The current value of RBBM_STATUS which shows what top level GPU
44 identified with an id number.
46 id
47 Ringbuffer ID (0 based index). Each ringbuffer in the section
48 will have its own unique id.
[all …]
/linux/include/linux/
H A Dvga_switcheroo.h2 * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs
39 * enum vga_switcheroo_handler_flags_t - handler flags bitmask
45 * GPU needs to train the link and communicate the link parameters to the
46 * inactive GPU (mediated by vga_switcheroo). The inactive GPU may then
47 * skip the AUX handshake and set up its output with these pre-calibrated
59 * enum vga_switcheroo_state - client power state
76 * enum vga_switcheroo_client_id - client identifier
78 * Determining the id requires the handler, so GPUs are given their
79 * true id in a delayed fashion in vga_switcheroo_enable()
94 * struct vga_switcheroo_handler - handler callbacks
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_gfx_if.h38 * Command ID must be between 0x00010000 and 0x000F0000.
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
53 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
57 /*-----------------------------------------------------------------------------
59 GPU Virtual Addresses.
64 * SRBM-to-PSP mailbox registers (total 8 registers).
73 … volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74 …volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) …
116 /* PSP boot config sub-commands */
[all …]
/linux/drivers/power/sequencing/
H A Dpwrseq-thead-gpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * T-HEAD TH1520 GPU Power Sequencer Driver
8 * This driver implements the power sequence for the Imagination BXM-4-64
9 * GPU on the T-HEAD TH1520 SoC. The sequence requires coordinating resources
10 * from both the sequencer's parent device node (clkgen_reset) and the GPU's
13 * The `match` function is used to acquire the GPU's resources when the
14 * GPU driver requests the "gpu-power" sequence target.
26 #include <dt-bindings/power/thead,th1520-power.h>
45 if (!ctx->clks || !ctx->gpu_reset) in pwrseq_thead_gpu_enable()
46 return -ENODEV; in pwrseq_thead_gpu_enable()
[all …]
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_crat.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2015-2022 Advanced Micro Devices, Inc.
33 /* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
34 * GPU processor ID are expressed with Bit[31]=1.
35 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
40 /* Return the next available gpu_processor_id and increment it for next GPU
41 * @total_cu_count - Total CUs present in the GPU including ones
172 /* L2 Data Cache per GPU (Total Tex Cache) */
215 /* L2 Data Cache per GPU (Total Tex Cache) */
258 /* L2 Data Cache per GPU (Total Tex Cache) */
[all …]
/linux/Documentation/devicetree/bindings/gpu/
H A Dvivante,gc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpu/vivante,gc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Vivante GPU
9 description: Vivante GPU core devices
12 - Lucas Stach <l.stach@pengutronix.de>
24 '#cooling-cells':
27 assigned-clock-parents: true
28 assigned-clock-rates: true
[all …]
/linux/drivers/interconnect/mediatek/
H A Dmt8183.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/interconnect-provider.h>
13 #include <dt-bindings/interconnect/mediatek,mt8183.h>
15 #include "icc-emi.h"
18 .name = "ddr-emi",
19 .id = SLAVE_DDR_EMI,
25 .id = MASTER_MCUSYS,
31 static struct mtk_icc_node gpu = { variable
32 .name = "gpu",
33 .id = MASTER_MFG,
[all …]
/linux/drivers/gpu/drm/xe/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
80 bool "Enable CPU to GPU address mirroring"
88 Enable this option if you want support for CPU to GPU address
121 Use "<pci-id>[,<pci-id>,...]" to force probe the xe for listed
126 Use "!" right before the ID to block the probe of the device. For
135 source "drivers/gpu/drm/xe/Kconfig.debug"
141 source "drivers/gpu/drm/xe/Kconfig.profile"
/linux/Documentation/gpu/rfc/
H A Di915_vm_bind.h1 /* SPDX-License-Identifier: MIT */
32 * Flag to opt-in for VM_BIND mode of binding during VM creation.
51 * struct drm_i915_gem_timeline_fence - An input or output timeline fence.
74 #define __I915_TIMELINE_FENCE_UNKNOWN_FLAGS (-(I915_TIMELINE_FENCE_SIGNAL << 1))
86 * struct drm_i915_gem_vm_bind - VA to object mapping to bind.
88 * This structure is passed to VM_BIND ioctl and specifies the mapping of GPU
98 * platform, for binding device local-memory objects, the @start, @offset and
102 * Error code -EINVAL will be returned if @start, @offset and @length are not
104 * -ENOSPC will be returned if the VA range specified can't be reserved.
111 /** @vm_id: VM (address space) id to bind */
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