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/linux/Documentation/devicetree/bindings/mtd/
H A Dgpmi-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/gpmi-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale General-Purpose Media Interface (GPMI)
10 - Han Xu <han.xu@nxp.com>
13 The GPMI nand controller provides an interface to control the NAND
14 flash chips. The device tree may optionally contain sub-nodes
21 - enum:
22 - fsl,imx23-gpmi-nand
[all …]
/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
19 #include <linux/dma/mxs-dma.h>
20 #include "gpmi-nand.h"
21 #include "gpmi-regs.h"
22 #include "bch-regs.h"
24 /* Resource names for the GPMI NAND driver. */
25 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
47 * SFTRST needs 3 GPMI clocks to settle, the reference manual in clear_poll_bit()
[all …]
H A Dgpmi-nand.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
13 #include <linux/dma-mapping.h>
26 * struct bch_geometry - BCH geometry description.
41 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
43 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
65 * struct boot_rom_geometry - Boot ROM geometry description.
94 * struct gpmi_nfc_hardware_timing - GPMI hardware timing parameters.
138 /* NAND Boot issue */
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
2 obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand.o
H A Dbch-regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Freescale GPMI NAND Flash Driver
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-seeed-npi-dev-board-nand.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "imx6ull-seeed-npi.dtsi"
10 #include "imx6ull-seeed-npi-dev-board.dtsi"
13 model = "Seeed NPi iMX6ULL Dev Board with NAND";
14 compatible = "seeed,imx6ull-seeed-npi-nand", "seeed,imx6ull-seeed-npi", "fsl,imx6ull";
17 &gpmi {
H A Dimx6ull-phytec-tauri-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
8 #include "imx6ull-phytec-tauri.dtsi"
11 model = "PHYTEC phyGate-Tauri i.MX6 UltraLite";
12 compatible = "phytec,imx6ull-phygate-tauri-nand",
13 "phytec,imx6ull-phygate-tauri",
14 "phytec,imx6ull-pcl063", "fsl,imx6ull";
17 /* NAND-Version */
18 &gpmi {
H A Dimx6ull-phytec-segin-lc-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx6ull-phytec-phycore-som.dtsi"
10 #include "imx6ull-phytec-segin.dtsi"
11 #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
12 #include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
15 model = "PHYTEC phyBOARD-Segin i.MX6 ULL Low Cost with NAND";
16 compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
17 "phytec,imx6ull-pcl063", "fsl,imx6ull";
32 &gpmi {
H A Dimx6dl-phytec-mira-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx6qdl-phytec-phycore-som.dtsi"
10 #include "imx6qdl-phytec-mira.dtsi"
11 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
12 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
13 #include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
16 model = "PHYTEC phyBOARD-Mira DualLite/Solo Carrier-Board with NAND";
17 compatible = "phytec,imx6dl-pbac06-nand", "phytec,imx6dl-pbac06",
18 "phytec,imx6qdl-pcm058", "fsl,imx6dl";
[all …]
H A Dimx6qp-phytec-mira-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Author: Enrico Scholz <enrico.scholz@sigma-chemnitz.de>
7 /dts-v1/;
9 #include "imx6qdl-phytec-phycore-som.dtsi"
10 #include "imx6qdl-phytec-mira.dtsi"
11 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
12 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
13 #include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
16 model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
17 compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06",
[all …]
H A Dimx6q-phytec-mira-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx6qdl-phytec-phycore-som.dtsi"
10 #include "imx6qdl-phytec-mira.dtsi"
11 #include "imx6qdl-phytec-mira-peb-eval-01.dtsi"
12 #include "imx6qdl-phytec-mira-peb-av-02.dtsi"
13 #include "imx6qdl-phytec-mira-peb-wlbt-05.dtsi"
16 model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
17 compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
18 "phytec,imx6qdl-pcm058", "fsl,imx6q";
[all …]
H A Dimx6ull-phytec-segin-ff-rdk-nand.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx6ull-phytec-phycore-som.dtsi"
10 #include "imx6ull-phytec-segin.dtsi"
11 #include "imx6ull-phytec-segin-peb-eval-01.dtsi"
12 #include "imx6ull-phytec-segin-peb-av-02.dtsi"
13 #include "imx6ull-phytec-segin-peb-wlbt-05.dtsi"
16 model = "PHYTEC phyBOARD-Segin i.MX6 ULL Full Featured with NAND";
17 compatible = "phytec,imx6ull-pbacd10-nand", "phytec,imx6ull-pbacd10",
18 "phytec,imx6ull-pcl063", "fsl,imx6ull";
[all …]
H A Dimx6ul-phytec-segin-ff-rdk-nand.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "imx6ul-phytec-phycore-som.dtsi"
10 #include "imx6ul-phytec-segin.dtsi"
11 #include "imx6ul-phytec-segin-peb-eval-01.dtsi"
12 #include "imx6ul-phytec-segin-peb-av-02.dtsi"
13 #include "imx6ul-phytec-segin-peb-wlbt-05.dtsi"
16 model = "PHYTEC phyBOARD-Segin i.MX6 UltraLite Full Featured with NAND";
17 compatible = "phytec,imx6ul-pbacd10-nand", "phytec,imx6ul-pbacd10",
18 "phytec,imx6ul-pcl063", "fsl,imx6ul";
[all …]
H A Dimx7s-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2016-2022 Toradex
7 #include "imx7-colibri.dtsi"
16 /* NAND */
17 &gpmi {
H A Dimx6ul-isiot-nand.dts1 // SPDX-License-Identifier: GPL-2.0 OR X11
7 /dts-v1/;
9 #include "imx6ul-isiot.dtsi"
12 model = "Engicam Is.IoT MX6UL NAND Starter kit";
13 compatible = "engicam,imx6ul-isiot", "fsl,imx6ul";
16 &gpmi {
H A Dimx6ull-myir-mys-6ulx-eval.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include "imx6ull-myir-mys-6ulx.dtsi"
12 model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
13 compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
16 &gpmi {
17 fsl,use-minimum-ecc;
H A Dimx7d-colibri.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2016-2022 Toradex
7 #include "imx7-colibri.dtsi"
23 cpu-supply = <&reg_DCDC2>;
26 /* NAND */
27 &gpmi {
34 vbus-supply = <&reg_usbh_vbus>;
H A Dimx6qdl-skov-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
10 stdout-path = &uart2;
19 mdio-gpio0 = &mdio;
20 nand = &gpmi;
28 iio-hwmon {
29 compatible = "iio-hwmon";
30 io-channels = <&adc 0>, /* 24V */
35 compatible = "gpio-leds";
[all …]
H A Dimx6ull-colibri-emmc-nonwifi.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include "imx6ull-colibri.dtsi"
11 mmc1 = &usdhc1; /* MMC 4-bit slot */
21 gpio-line-names = "SODIMM_8",
54 gpio-line-names = "SODIMM_55",
79 gpio-line-names = "SODIMM_56",
111 gpio-line-names = "",
143 gpio-line-names = "SODIMM_43",
157 /* NAND */
158 &gpmi {
[all …]
H A Dimx6ulz-bsh-smm-m2.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/input.h>
13 compatible = "bsh,imx6ulz-bsh-smm-m2", "fsl,imx6ull", "fsl,imx6ulz";
16 stdout-path = &uart4;
19 usdhc2_pwrseq: usdhc2-pwrseq {
20 compatible = "mmc-pwrseq-simple";
21 reset-gpios = <&gpio2 21 GPIO_ACTIVE_LOW>;
25 &gpmi {
26 pinctrl-names = "default";
[all …]
H A Dimx6ul-phytec-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/pwm/pwm.h>
12 model = "PHYTEC phyCORE-i.MX6 UltraLite";
13 compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
16 stdout-path = &uart1;
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpioleds_som>;
31 compatible = "gpio-leds";
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx23-pinfunc.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&icoll>;
14 * pre-existing /chosen node to be available to insert the
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,arm926ej-s";
42 compatible = "simple-bus";
[all …]
H A Dimx28-eukrea-mbmx283lc.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Module contains : i.MX282 + 64MB DDR2 + NAND + Ethernet PHY + RTC
11 /dts-v1/;
12 #include "imx28-eukrea-mbmx28lc.dtsi"
24 &gpmi {
25 pinctrl-names = "default";
26 pinctrl-0 = <&gpmi_pins_a>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&i2c0_pins_a>;
43 phy-mode = "rmii";
[all …]
H A Dimx28.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include "imx28-pinfunc.h"
9 #address-cells = <1>;
10 #size-cells = <1>;
12 interrupt-parent = <&icoll>;
15 * pre-existing /chosen node to be available to insert the
42 #address-cells = <1>;
43 #size-cells = <0>;
46 compatible = "arm,arm926ej-s";
[all …]
H A Dimx28-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
10 compatible = "fsl,imx28-evk", "fsl,imx28";
18 reg_3p3v: regulator-3p3v {
19 compatible = "regulator-fixed";
20 regulator-name = "3P3V";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
23 regulator-always-on;
26 reg_vddio_sd0: regulator-vddio-sd0 {
[all …]

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