| /freebsd/sys/contrib/device-tree/src/arm64/hisilicon/ |
| H A D | hi3798cv200.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
8 #include <dt-bindings/clock/histb-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/reset/ti-syscon.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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| H A D | hi6220.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/reset/hisi,hi6220-resets.h>
10 #include <dt-bindings/clock/hi6220-clock.h>
11 #include <dt-bindings/pinctrl/hisi.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
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| H A D | hikey960-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range { label
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
23 /* pin base, nr pins & gpio function */
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| H A D | hikey970-pinctrl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range { label
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | pinctrl-single.txt | 1 One-register-per-pin type device tree based pinctrl driver
4 - compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
8 - reg : offset and length of the register set for the mux registers
10 - #pinctrl-cells : number of cells in addition to the index, set to 1
11 or 2 for pinctrl-single,pins and set to 2 for pinctrl-single,bits
13 - pinctrl-single,register-width : pinmux register access width in bits
15 - pinctrl-single,function-mask : mask of allowed pinmux function bits
19 - pinctrl-single,function-off : function off mode for disabled state if
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| H A D | pinctrl-single.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
14 range of pin control registers can vary from one to many for each controller
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
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| H A D | ingenic,pinctrl.txt | 3 Please refer to pinctrl-bindings.txt in this directory for details of the
7 For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
9 GPIO port configuration registers and it is typical to refer to pins using the
10 naming scheme "PxN" where x is a character identifying the GPIO port with
12 pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
13 PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
14 contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
15 jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
19 --------------------
21 - compatible: One of:
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| H A D | microchip,sparx5-sgpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microsemi/Microchip Serial GPIO controller
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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| /freebsd/sys/contrib/device-tree/src/arm/hisilicon/ |
| H A D | hi3620.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
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| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | adi,ad7606.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7605-4.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7616.pdf
22 - adi,ad7605-4
23 - adi,ad7606-4
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio.txt | 1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
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| H A D | gpio-eic-sprd.txt | 6 controller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and
7 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
10 The EIC-debounce sub-module provides up to 8 source input signal
12 stable status (millisecond resolution) and a single-trigger mechanism
13 is introduced into this sub-module to enhance the input event detection
14 reliability. In addition, this sub-module's clock can be shut off
15 automatically to reduce power dissipation. Moreover the debounce range
19 The EIC-latch sub-module is used to latch some special power down signals
20 and generate interrupts, since the EIC-latch does not depend on the APB
23 The EIC-async sub-module uses a 32kHz clock to capture the short signals
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| /freebsd/sys/contrib/device-tree/Bindings/iio/addac/ |
| H A D | adi,ad74115.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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| /freebsd/sys/contrib/device-tree/src/arm/marvell/ |
| H A D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
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| H A D | armada-xp-mv78260.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
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| H A D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
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| /freebsd/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am62p-main.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,am62-usb";
14 clock-names = "ref";
15 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
27 interrupt-names = "host", "peripheral";
28 maximum-speed = "high-speed";
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| /freebsd/sys/contrib/device-tree/Bindings/leds/backlight/ |
| H A D | pwm-backlight.txt | 1 pwm-backlight bindings
4 - compatible: "pwm-backlight"
5 - pwms: OF device-tree PWM specification (see PWM binding[0])
6 - power-supply: regulator for supply voltage
9 - pwm-names: a list of names for the PWM devices specified in the
11 - enable-gpios: contains a single GPIO specifier for the GPIO which enables
12 and disables the backlight (see GPIO binding[1])
13 - post-pwm-on-delay-ms: Delay in ms between setting an initial (non-zero) PWM
14 and enabling the backlight using GPIO.
15 - pwm-off-delay-ms: Delay in ms between disabling the backlight using GPIO
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| /freebsd/sys/contrib/device-tree/Bindings/iio/dac/ |
| H A D | ad5758.txt | 4 - compatible: Must be "adi,ad5758"
5 - reg: SPI chip select number for the device
6 - spi-max-frequency: Max SPI frequency to use (< 50000000)
7 - spi-cpha: is the only mode that is supported
11 - adi,dc-dc-mode: Mode of operation of the dc-to-dc converter
19 In this mode, the VDPC+ voltage is user-programmable to
36 - adi,range-microvolt: Voltage output range
38 * <0 5000000>: 0 V to 5 V voltage range
39 * <0 10000000>: 0 V to 10 V voltage range
40 * <(-5000000) 5000000>: ±5 V voltage range
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| H A D | adi,ad5766.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Nuno Sá <nuno.sa@analog.com>
16 https://www.analog.com/media/en/technical-documentation/data-sheets/ad5766-5767.pdf
21 - adi,ad5766
22 - adi,ad5767
24 output-range-microvolts:
25 $ref: /schemas/types.yaml#/definitions/int32-array
27 description: Select converter output range.
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| /freebsd/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | ti,tps62360.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laxman Dewangan <ldewangan@nvidia.com>
13 The TPS6236x are a family of step down dc-dc converter with
14 an input voltage range of 2.5V to 5.5V. The devices provide
15 up to 3A peak load current, and an output voltage range of
22 - $ref: regulator.yaml#
27 - ti,tps62360
28 - ti,tps62361
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| H A D | pwm-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/pwm-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
11 - Lee Jones <lee@kernel.org>
12 - Alexandre Courbot <acourbot@nvidia.com>
19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
23 is given to the user if the assumptions made in continuous-voltage mode do
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| /freebsd/sys/contrib/device-tree/src/arm64/allwinner/ |
| H A D | sun50i-h700-anbernic-rg35xx-h.dts | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
7 #include "sun50i-h700-anbernic-rg35xx-plus.dts"
11 compatible = "anbernic,rg35xx-h", "allwinner,sun50i-h700";
13 adc-joystick {
14 compatible = "adc-joystick";
15 io-channels = <&adc_mux 0>,
19 pinctrl-0 = <&joy_mux_pin>;
20 pinctrl-names = "default";
21 poll-interval = <60>;
22 #address-cells = <1>;
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| /freebsd/sys/arm/ti/ |
| H A D | ti_pinmux.c | 34 * Exposes pinmux module to pinctrl-compatible interface
67 { -1, 0 }
73 bus_space_read_2((sc)->sc_bst, (sc)->sc_bsh, (reg))
75 bus_space_write_2((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
77 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
79 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
82 * ti_padconf_devmap - Array of pins, should be defined one per SoC
91 * ti_pinmux_padconf_from_name - searches the list of pads and returns entry
103 padconf = ti_pinmux_dev->padconf; in ti_pinmux_padconf_from_name()
104 while (padconf->ballname != NULL) { in ti_pinmux_padconf_from_name()
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| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3566-anbernic-rg353x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include "rk3566-anbernic-rgxx3.dtsi"
11 adc-joystick {
12 compatible = "adc-joystick";
13 io-channels = <&adc_mux 0>,
17 pinctrl-0 = <&joy_mux_en>;
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