Home
last modified time | relevance | path

Searched +full:gpio +full:- +full:mpp (Results 1 – 25 of 43) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dqcom,pmic-mpp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm PMIC Multi-Purpose Pin (MPP) block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This binding describes the MPP block(s) found in the 8xxx series of
19 - items:
20 - enum:
21 - qcom,pm8019-mpp
[all …]
H A Dqcom,pmic-mpp.txt1 Qualcomm PMIC Multi-Purpose Pin (MPP) block
3 This binding describes the MPP block(s) found in the 8xxx series
6 - compatible:
10 "qcom,pm8018-mpp",
11 "qcom,pm8019-mpp",
12 "qcom,pm8038-mpp",
13 "qcom,pm8058-mpp",
14 "qcom,pm8821-mpp",
15 "qcom,pm8841-mpp",
16 "qcom,pm8916-mpp",
[all …]
H A Dmarvell,orion-pinctrl.txt1 * Marvell Orion SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f5181-pinctrl",
8 "marvell,88f5181l-pinctrl",
9 "marvell,88f5182-pinctrl",
10 "marvell,88f5281-pinctrl"
12 - reg: two register areas, the first one describing the first two
13 contiguous MPP registers, and the second one describing the single
14 final MPP register, separated from the previous one.
16 Available mpp pins/groups and functions:
[all …]
H A Dmarvell,dove-pinctrl.txt1 * Marvell Dove SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
12 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
19 mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
20 mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
[all …]
H A Dmarvell,armada-375-pinctrl.txt1 * Marvell Armada 375 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
18 mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)
19 mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)
[all …]
H A Dmarvell,armada-xp-pinctrl.txt1 * Marvell Armada XP SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
14 Note: brackets (x) are not part of the mpp name for marvell,function and given
21 mpp0 0 gpio, ge0(txclkout), lcd(d0)
22 mpp1 1 gpio, ge0(txd0), lcd(d1)
23 mpp2 2 gpio, ge0(txd1), lcd(d2)
[all …]
H A Dmarvell,armada-370-pinctrl.txt1 * Marvell Armada 370 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
11 Note: brackets (x) are not part of the mpp name for marvell,function and given
16 mpp0 0 gpio, uart0(rxd)
18 mpp2 2 gpio, i2c0(sck), uart0(txd)
19 mpp3 3 gpio, i2c0(sda), uart0(rxd)
20 mpp4 4 gpio, vdd(cpu-pd)
[all …]
H A Dmarvell,armada-38x-pinctrl.txt1 * Marvell Armada 380/385 SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
13 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
[all …]
H A Dmarvell,armada-39x-pinctrl.txt1 * Marvell Armada 39x SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
13 Note: brackets (x) are not part of the mpp name for marvell,function and given
18 mpp0 0 gpio, ua0(rxd)
19 mpp1 1 gpio, ua0(txd)
20 mpp2 2 gpio, i2c0(sck)
[all …]
H A Dmarvell,armada-98dx3236-pinctrl.txt1 * Marvell 98dx3236 pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8 - reg: register specifier of MPP registers
15 mpp1 1 gpio, spi0(miso), dev(ad9)
17 mpp3 3 gpio, spi0(cs0), dev(ad11)
18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
19 mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs)
21 mpp7 7 gpio, sd0(d0), dev(ale0)
22 mpp8 8 gpio, sd0(d1), dev(ale1)
[all …]
H A Dmarvell,kirkwood-pinctrl.txt1 * Marvell Kirkwood SoC pinctrl driver for mpp
3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
16 Available mpp pins/groups and functions:
17 Note: brackets (x) are not part of the mpp name for marvell,function and given
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dorion5x-rd88f5182-nas.dts1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include "orion5x-mv88f5182.dtsi"
11 compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
20 stdout-path = &uart0;
30 gpio-leds {
31 compatible = "gpio-leds";
32 pinctrl-0 = <&pmx_debug_led>;
[all …]
/freebsd/sys/dts/
H A Dbindings-mpp.txt2 * Multi purpose pin (MPP) configuration.
6 - pin-map : array of pin configurations. Each pin is defined by 2 cells,
7 respectively: <pin> <function>. Pins not specified in the pin-map property
8 are assumed to have default value of <function> = 0, which means GPIO.
10 - pin : pin number.
12 - function : function ID of the pin according to the assignment tables in
14 MPP unit incarnation.
16 - pin-count: number of the physical MPP connections on the SOC (depending on
17 the model it can be 24-50, or possibly else in future devices).
21 mpp@10000 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dpmi8994.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/spmi/spmi.h>
8 compatible = "qcom,pmi8994", "qcom,spmi-pmic";
10 #address-cells = <1>;
11 #size-cells = <0>;
13 pmi8994_gpios: gpio@c000 {
14 compatible = "qcom,pmi8994-gpio", "qcom,spmi-gpio";
16 gpio-controller;
17 gpio-ranges = <&pmi8994_gpios 0 0 10>;
[all …]
H A Dpm8950.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include <dt-bindings/iio/qcom,spmi-vadc.h>
9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
12 #include <dt-bindings/spmi/spmi.h>
16 compatible = "qcom,pm8950", "qcom,spmi-pmic";
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "qcom,pm8916-pon";
[all …]
H A Dpmi8950.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/iio/qcom,spmi-vadc.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/spmi/spmi.h>
10 compatible = "qcom,pmi8950", "qcom,spmi-pmic";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "qcom,spmi-vadc";
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
H A Dpm8994.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/spmi/spmi.h>
8 thermal-zones {
9 pm8994-thermal {
10 polling-delay-passive = <250>;
12 thermal-sensors = <&pm8994_temp>;
15 pm8994_alert0: pm8994-alert0 {
[all …]
H A Dpm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/spmi/spmi.h>
8 thermal-zones {
9 pm8916-thermal {
10 polling-delay-passive = <100>;
12 thermal-sensors = <&pm8916_temp>;
39 compatible = "qcom,pm8916", "qcom,spmi-pmic";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-pma8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/spmi/spmi.h>
9 compatible = "qcom,pma8084", "qcom,spmi-pmic";
11 #address-cell
[all...]
H A Dpma8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/spmi/spmi.h>
10 compatible = "qcom,pma8084", "qcom,spmi-pmic";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "qcom,pm8941-rtc";
19 reg-names = "rtc", "alarm";
[all …]
H A Dqcom-pm8841.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/interrupt-controller/irq.h>
3 #include <dt-bindings/spmi/spmi.h>
7 thermal-zones {
8 pm8841-thermal {
9 polling-delay-passive = <100>;
10 polling-delay = <0>;
11 thermal-sensors = <&pm8841_temp>;
39 compatible = "qcom,pm8841", "qcom,spmi-pmic";
41 #address-cells = <1>;
[all …]
H A Dqcom-pm8226.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-binding
[all...]
H A Dqcom-pm8941.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/iio/qcom,spmi-vadc.h>
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/spmi/spmi.h>
8 thermal-zones {
9 pm8941-therma
[all...]
/freebsd/sys/contrib/device-tree/Bindings/arm/marvell/
H A Dap80x-system-controller.txt6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
[all …]
/freebsd/sys/arm/mv/
H A Dmv_armv7_machdep.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (c) 1994-1998 Mark Brinicombe.
122 * for all A38x-based platforms only. in mv_busdma_tag_init()
124 if ((node = OF_finddevice("/")) == -1){ in mv_busdma_tag_init()
153 int mpp[MPP_PIN_MAX]; in platform_mpp_init() local
165 * Try to access the MPP node directly i.e. through /aliases/mpp. in platform_mpp_init()
167 if ((node = OF_finddevice("mpp")) != -1) in platform_mpp_init()
168 if (ofw_bus_node_is_compatible(node, "mrvl,mpp")) in platform_mpp_init()
173 if ((node = OF_finddevice("/")) == -1) in platform_mpp_init()
[all …]

12