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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-dhcom-som.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 #include "imx6ull-dhcor-som.dtsi"
10 /delete-property/ spi2;
11 /delete-property/ spi3;
28 stdout-path = "serial0:115200n8";
31 reg_ext_3v3_ref: regulator-ext-3v3-ref {
32 compatible = "regulator-fixed";
33 regulator-always-on;
34 regulator-max-microvolt = <3300000>;
35 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx6ull-dhcor-maveo-box.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 * DHCR-iMX6ULL-C080-R051-SPI-WBT-I-01LG
8 * DHCOR PCB number: 578-200 or newer
9 * maveo box PCB number: 525-200 or newer
12 /dts-v1/;
14 #include "imx6ull-dhcor-som.dtsi"
18 compatible = "marantec,imx6ull-dhcor-maveo-box", "dh,imx6ull-dhcor-som",
28 stdout-path = "serial0:115200n8";
31 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
32 compatible = "regulator-fixed";
[all …]
H A Dimx6ull-seeed-npi-dev-board.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/gpio/gpio.h>
11 stdout-path = &uart1;
14 gpio_buttons: gpio-keys {
15 compatible = "gpio-keys";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_button>;
19 button-0 {
23 wakeup-source;
27 gpio-leds {
[all …]
H A Dimx6ull-dhcor-som.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 #include <dt-bindings/clock/imx6ul-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include <dt-bindings/regulator/dlg,da9063-regulator.h>
16 /delete-property/ mmc0;
17 /delete-property/ mmc1;
21 /* Appropriate memory size will be filled by U-Boot */
[all …]
H A Dimx6ull-dhcom-som-cfg-sdcard.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
11 * GPIO H and GPIO I will be available
18 * pwrseq node is also deleted in order to ensure that GPIO H is released.
21 /delete-node/ &brcmf;
22 /delete-node/ &usdhc1_pwrseq;
23 /delete-node/ &bluetooth;
36 reg_sd1_vmmc: regulator-sd1-vmmc {
37 compatible = "regulator-fixed";
38 regulator-max-microvolt = <3300000>;
39 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-data-modul-edm-sbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/net/qca-ar803x.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
22 stdout-path = &uart3;
32 compatible = "pwm-backlight";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
[all …]
H A Dimx8mp-dhcom-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
28 gpio = <&ioexp 2 GPIO_ACTIVE_LOW>;
29 regulator-always-on;
30 regulator-boot-on;
31 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx8mm-data-modul-edm-sbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/net/qca-ar803x.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
22 stdout-path = &uart3;
32 compatible = "pwm-backlight";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
[all …]
H A Dimx8mm-innocomm-wb15.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 reg_modem: regulator-modem {
11 compatible = "regulator-fixed";
12 pinctrl-names = "default";
13 pinctrl-0 = <&pinctrl_modem_regulator>;
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
16 regulator-name = "epdev_on";
17 gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
[all …]
H A Dimx8mm-emcon.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
13 stdout-path = &uart1;
17 compatible = "gpio-leds";
18 pinctrl-names = "default";
19 pinctrl-0 = <&pinctrl_gpio_led>;
21 led-green {
24 default-state = "on";
25 linux,default-trigger = "heartbeat";
28 led-red {
[all …]
H A Dimx8mm-emtop-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/usb/pd.h>
15 model = "Emtop Embedded Solutions i.MX8M Mini SOM-IMX8MMLPD4 SoM";
16 compatible = "ees,imx8mm-emtop-som", "fsl,imx8mm";
19 stdout-path = &uart2;
23 compatible = "gpio-leds";
24 pinctrl-names = "default";
[all …]
H A Dimx8mm-innocomm-wb15-evk.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mm-innocomm-wb15.dtsi"
12 model = "InnoComm WB15-EVK";
13 compatible = "innocomm,wb15-evk", "fsl,imx8mm";
16 stdout-path = &uart2;
20 compatible = "gpio-leds";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_gpio_leds>;
24 led-0 {
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-rt305x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-ralink/ralink_regs.h>
4 #include <asm/mach-ralink/rt305x.h>
8 #include "pinctrl-mtmips.h"
41 FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
42 FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
43 FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
67 GRP("i2c", i2c_grp, 1, RT305X_GPIO_MODE_I2C),
68 GRP("spi", spi_grp, 1, RT305X_GPIO_MODE_SPI),
69 GRP("uartf", uartf_grp, RT305X_GPIO_MODE_UART0_MASK,
[all …]
H A Dpinctrl-rt3883.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "pinctrl-mtmips.h"
49 FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
50 FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
51 FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
59 FUNC("pci-dev", 0, 40, 32),
60 FUNC("pci-host2", 1, 40, 32),
61 FUNC("pci-host1", 2, 40, 32),
62 FUNC("pci-fnc", 3, 40, 32)
68 GRP("i2c", i2c_grp, 1, RT3883_GPIO_MODE_I2C),
[all …]
H A Dpinctrl-mt7620.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "pinctrl-mtmips.h"
73 FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
74 FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
75 FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
91 GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
92 GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
94 GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
95 GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
100 GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
[all …]
/linux/drivers/pinctrl/meson/
H A Dpinctrl-meson8-pmx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 #define GROUP(grp, r, b) \ argument
24 .name = #grp, \
25 .pins = grp ## _pins, \
26 .num_pins = ARRAY_SIZE(grp ## _pins), \
32 #define GPIO_GROUP(gpio) \ argument
34 .name = #gpio, \
35 .pins = (const unsigned int[]){ gpio }, \
H A Dpinctrl-meson-axg-pmx.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
42 #define GROUP(grp, f) \ argument
44 .name = #grp, \
45 .pins = grp ## _pins, \
46 .num_pins = ARRAY_SIZE(grp ## _pins), \
52 #define GPIO_GROUP(gpio) \ argument
54 .name = #gpio, \
55 .pins = (const unsigned int[]){ gpio }, \
/linux/drivers/pinctrl/intel/
H A Dpinctrl-intel.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel pinctrl/GPIO core driver.
13 #include <linux/gpio/driver.h>
25 #include <linux/pinctrl/pinconf-generic.h>
29 #include <linux/platform_data/x86/pwm-lpss.h>
32 #include "pinctrl-intel.h"
92 * 0 0 0 -
127 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
128 #define padgroup_offset(g, p) ((p) - (g)->base)
132 __ci < pctrl->ncommunities && (community = &pctrl->communities[__ci]); \
[all …]
H A Dpinctrl-lynxpoint.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Lynxpoint PCH pinctrl/GPIO driver
14 #include <linux/gpio/driver.h>
25 #include <linux/pinctrl/pinconf-generic.h>
30 #include "pinctrl-intel.h"
147 /* LynxPoint chipset has support for 95 GPIO pins */
168 #define USE_SEL_MASK GENMASK(1, 0) /* 0: Native, 1: GPIO, ... */
181 * per gpio specific registers. The bitmapped registers are in chunks of
184 * per gpio specific registers consist of two 32bit registers per gpio
190 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-at91.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 #include <linux/gpio/driver.h>
29 #include "pinctrl-at91.h"
38 * struct at91_gpio_chip: at91 gpio chip
39 * @chip: gpio chip
40 * @range: gpio range
49 * @id: gpio chip identifier
114 * struct at91_pmx_func - describes AT91 pinmux functions
134 * struct at91_pmx_pin - describes an At91 pin mux
[all …]
H A Dpinctrl-st.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/gpio/driver.h>
100 * (direction, retime-type, retime-clk, retime-delay)
102 * +----------------+
103 *[31:28]| reserved-3 |
104 * +----------------+-------------
106 * +----------------+ v
108 * +----------------+ ^
110 * +----------------+-------------
111 *[24] | reserved-2 |
[all …]
/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <linux/gpio/driver.h>
24 #include "pinctrl-mvebu.h"
64 *config = (readl(data->base + off) >> shift) & MVEBU_MPP_MASK; in mvebu_mmio_mpp_ctrl_get()
76 reg = readl(data->base + off) & ~(MVEBU_MPP_MASK << shift); in mvebu_mmio_mpp_ctrl_set()
77 writel(reg | (config << shift), data->base + off); in mvebu_mmio_mpp_ctrl_set()
86 for (n = 0; n < pctl->num_groups; n++) { in mvebu_pinctrl_find_group_by_pid()
87 if (pid >= pctl->groups[n].pins[0] && in mvebu_pinctrl_find_group_by_pid()
88 pid < pctl->groups[n].pins[0] + in mvebu_pinctrl_find_group_by_pid()
[all …]
/linux/drivers/pinctrl/nxp/
H A Dpinctrl-s32cc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2017-2022,2024 NXP
7 * Copyright 2015-2016 Freescale Semiconductor, Inc.
12 #include <linux/gpio/driver.h>
28 #include "../pinctrl-utils.h"
29 #include "pinctrl-s32.h"
70 * Holds pin configuration for GPIO's.
71 * @pin_id: Pin ID for this GPIO
73 * @list: Linked list entry for each gpio pin
93 * @gpio_configs: Saved configurations for GPIO pins
[all …]
/linux/drivers/pinctrl/qcom/
H A Dpinctrl-qdf2xxx.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * GPIO and pin control functions on this SOC are handled by the "TLMM"
6 * device. The driver which controls this device is pinctrl-msm.c. Each
8 * with pinctrl-msm.c. This means that all TLMM drivers are pin control
11 * This pin control driver is intended to be used only an ACPI-enabled
14 * a GPIO-only driver. The alternative is to duplicate the GPIO code of
15 * pinctrl-msm.c into another driver.
23 #include "pinctrl-msm.h"
25 /* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
28 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
[all …]
/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx1-core.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Based on pinctrl-imx.c:
29 #include "pinctrl-imx1.h"
67 * configuration A, input configuration B, GPIO in use and data direction.
81 return ipctl->base + port * MX1_PORT_STRIDE; in imx1_mem()
101 dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n", in imx1_write_2bit()
161 const struct imx1_pin_group *grp = NULL; in imx1_pinctrl_find_group_by_name() local
164 for (i = 0; i < info->ngroups; i++) { in imx1_pinctrl_find_group_by_name()
165 if (!strcmp(info->groups[i].name, name)) { in imx1_pinctrl_find_group_by_name()
166 grp = &info->groups[i]; in imx1_pinctrl_find_group_by_name()
[all …]

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