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/linux/drivers/clk/mediatek/
H A Dclk-mt2701-eth.c27 GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,msm8226-pinctrl.yaml67 gp0_clk, gp1_clk, sdc3, wlan ]
H A Dqcom,apq8084-pinctrl.yaml84 gp0_clk, gp1_clk, gpio, hdmi_cec, hdmi_ddc, hdmi_dtest,
/linux/include/dt-bindings/clock/
H A Dqcom,gcc-ipq806x.h204 #define GP1_CLK 195 macro
H A Dqcom,gcc-msm8660.h233 #define GP1_CLK 224 macro
H A Dqcom,gcc-mdm9615.h259 #define GP1_CLK 249 macro
H A Dqcom,gcc-msm8960.h257 #define GP1_CLK 249 macro
/linux/drivers/clk/qcom/
H A Dgcc-mdm9615.c797 static struct clk_branch gp1_clk = { variable
804 .name = "gp1_clk",
1645 [GP1_CLK] = &gp1_clk.clkr,
H A Dgcc-msm8660.c1437 static struct clk_branch gp1_clk = { variable
1444 .name = "gp1_clk",
2565 [GP1_CLK] = &gp1_clk.clkr,
H A Dgcc-ipq806x.c1222 static struct clk_branch gp1_clk = { variable
1229 .name = "gp1_clk",
3104 [GP1_CLK] = &gp1_clk.clkr,