/linux/arch/arm64/boot/dts/broadcom/ |
H A D | bcm2712.dtsi | 10 interrupt-parent = <&gicv2>; 266 gicv2: interrupt-controller@7fff9000 { label 452 interrupt-parent = <&gicv2>; 457 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 458 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 459 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 460 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-parent = <&gicv2>; 494 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 495 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, [all …]
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/linux/Documentation/virt/kvm/devices/ |
H A D | arm-vgic.rst | 17 guest GICv2 through this interface. For information on creating a guest GICv3 19 create both a GICv3 and GICv2 device on the same VM. 58 GICv2 specs. Getting or setting such a register has the same effect as 65 GICv2 is changed in a way directly observable by the guest or userspace. 92 defined in the GICv2 specs. Getting or setting such a register has the 96 fixed format for our implementation that fits with the model of a "GICv2 112 similar to GICv2's GICH_APR.
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/linux/arch/arm64/boot/dts/arm/ |
H A D | foundation-v8-psci.dts | 4 * ARMv8 Foundation model DTS (GICv2+PSCI configuration) 8 #include "foundation-v8-gicv2.dtsi"
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H A D | foundation-v8.dts | 5 * ARMv8 Foundation model DTS (GICv2 configuration) 9 #include "foundation-v8-gicv2.dtsi"
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H A D | foundation-v8-gicv2.dtsi | 4 * ARMv8 Foundation model DTS (GICv2 configuration)
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/linux/Documentation/devicetree/bindings/pci/ |
H A D | brcm,stb-pcie.yaml | 202 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 203 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 204 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH 205 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
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/linux/arch/arm64/kvm/vgic/ |
H A D | vgic-mmio-v2.c | 20 * Revision 1: Report GICv2 interrupts as group 0 instead of group 1 370 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_read_apr() 382 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_read_apr() 396 /* GICv2 hardware systems support max. 32 groups */ in vgic_mmio_write_apr() 408 /* GICv3 only uses ICH_AP1Rn for memory mapped (GICv2) guests */ in vgic_mmio_write_apr()
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H A D | vgic-v2.c | 194 /* The GICv2 LR only holds five bits of priority. */ in vgic_v2_populate_lr() 343 kvm_err("GICv2 not supported in protected mode\n"); in vgic_v2_probe() 382 kvm_err("Cannot register GICv2 KVM device\n"); in vgic_v2_probe()
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H A D | vgic-mmio.c | 323 * GICv2 SGIs are terribly broken. We can't restore in __set_pending() 409 * More fun with GICv2 SGIs! If we're clearing one of them in __clear_pending() 466 * For GICv2 private interrupts we don't have to do anything because 570 * The GICv2 architecture indicates that the source CPUID for in vgic_mmio_change_active() 578 * for a GICv2 VM on some GIC implementations. Oh well. in vgic_mmio_change_active()
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H A D | vgic.h | 152 * state to userspace can generate either GICv2 or GICv3 CPU interface
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/linux/drivers/irqchip/ |
H A D | irq-gic.c | 897 .name = "GICv2", 1299 * first page of a GICv2. in gic_check_eoimode() 1305 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode() 1314 * The first page was that of a GICv2, and in gic_check_eoimode() 1316 * to be a GICv2, and update the mapping. in gic_check_eoimode() 1318 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode() 1326 * We detected *two* initial GICv2 pages in a in gic_check_eoimode() 1327 * row. Could be a GICv2 aliased over two 64kB in gic_check_eoimode() 1335 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode() 1343 * Verify that we have the first 4kB of a GICv2 in gic_check_eoimode() [all …]
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H A D | irq-gic-v3.c | 992 /* Extended SPI range, not handled by the GICv2/GICv3 common code */ in gic_dist_init()
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/linux/arch/arm/boot/dts/broadcom/ |
H A D | bcm2711.dtsi | 13 interrupt-parent = <&gicv2>; 56 gicv2: interrupt-controller@40041000 { label 564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 566 <0 0 0 2 &gicv2 GIC_SPI 144 568 <0 0 0 3 &gicv2 GIC_SPI 145 570 <0 0 0 4 &gicv2 GIC_SPI 146
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/linux/include/linux/irqchip/ |
H A D | arm-vgic-info.h | 14 /* Full GICv2 */
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H A D | arm-gic-v3.h | 50 * Those registers are actually from GICv2, but the spec demands that they 580 /* These are for GICv2 emulation only */
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/linux/Documentation/devicetree/bindings/gpio/ |
H A D | gpio-xgene-sb.txt | 12 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
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/linux/arch/arm64/kvm/hyp/ |
H A D | vgic-v3-sr.c | 264 * Group0 interrupt (as generated in GICv2 mode) to be in __vgic_v3_activate_traps() 422 * - [63] MMIO (GICv2) capable 430 * To check whether we have a MMIO-based (GICv2 compatible) in __vgic_v3_get_gic_config() 494 * If dealing with a GICv2 emulation on GICv3, VMCR_EL2.VFIQen in __vgic_v3_restore_vmcr_aprs()
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/linux/Documentation/translations/zh_CN/arch/arm64/ |
H A D | booting.txt | 205 - 设备树(DT)或 ACPI 表必须描述一个 GICv2 中断控制器。
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/linux/Documentation/translations/zh_TW/arch/arm64/ |
H A D | booting.txt | 209 - 設備樹(DT)或 ACPI 表必須描述一個 GICv2 中斷控制器。
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/linux/Documentation/arch/arm64/ |
H A D | booting.rst | 253 - The DT or ACPI tables must describe a GICv2 interrupt controller.
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/linux/drivers/vfio/pci/ |
H A D | vfio_pci_core.c | 1782 * regions like the GICv2 VCPU interface can trigger uncontained in vfio_pci_core_mmap()
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/linux/Documentation/virt/kvm/ |
H A D | api.rst | 860 On arm64, a GICv2 is created. Any other GIC versions require the usage of 861 KVM_CREATE_DEVICE, which also supports creating a GICv2. Using 862 KVM_CREATE_DEVICE is preferred over KVM_CREATE_IRQCHIP for GICv2.
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/linux/Documentation/admin-guide/ |
H A D | kernel-parameters.txt | 2525 of a GICv2 controller even if the memory range
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