Searched full:gicv2 (Results 1 – 10 of 10) sorted by relevance
199 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH200 0 0 0 2 &gicv2 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH201 0 0 0 3 &gicv2 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH202 0 0 0 4 &gicv2 GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
4 * ARMv8 Foundation model DTS (GICv2+PSCI configuration)8 #include "foundation-v8-gicv2.dtsi"
5 * ARMv8 Foundation model DTS (GICv2 configuration)9 #include "foundation-v8-gicv2.dtsi"
4 * ARMv8 Foundation model DTS (GICv2 configuration)
13 interrupt-parent = <&gicv2>;56 gicv2: interrupt-controller@40041000 { label566 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143568 <0 0 0 2 &gicv2 GIC_SPI 144570 <0 0 0 3 &gicv2 GIC_SPI 145572 <0 0 0 4 &gicv2 GIC_SPI 146
101 For GICv2 with virtualization extensions, additional regions are202 // GICv2
10 interrupt-parent = <&gicv2>;259 gicv2: interrupt-controller@7fff9000 { label
12 | (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N
86 /* We are using GICv2 register naming */1308 * GICv2m support -- the GICv2 MSI/MSI-X controller.
1021 * GICv2 backwards compatibility is not implemented so in dist_ctlr_write()