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/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-aemv8a.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
101 gic: interrupt-controller@2c001000 { label
102 compatible = "arm,gic-400", "arm,cortex-a15-gic";
141 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfoundation-v8.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
138 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
139 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfvp-base-revc.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
222 gic: interrupt-controller@2f000000 { label
223 compatible = "arm,gic-v3";
238 compatible = "arm,gic-v3-its";
338 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
339 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
340 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
341 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
375 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Djuno-base.dtsi69 gic: interrupt-controller@2c010000 { label
70 compatible = "arm,gic-400", "arm,cortex-a15-gic";
83 compatible = "arm,gic-v2m-frame";
89 compatible = "arm,gic-v2m-frame";
95 compatible = "arm,gic-v2m-frame";
101 compatible = "arm,gic-v2m-frame";
703 interrupt-map = <0 0 0 1 &gic 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
704 <0 0 0 2 &gic 0 GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
705 <0 0 0 3 &gic 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
706 <0 0 0 4 &gic 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/linux/drivers/irqchip/
H A Dirq-gic.c5 * Interrupt architecture for the GIC:
42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
114 * The GIC mapping of CPU interfaces does not necessarily match
116 * by the GIC itself.
309 pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16); in gic_set_type()
318 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
337 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
338 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
353 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
[all …]
H A Dirq-gic-pm.c9 #include <linux/irqchip/arm-gic.h>
28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local
39 * want to restore the GIC on the very first resume. So if in gic_runtime_resume()
42 if (!gic) in gic_runtime_resume()
45 gic_dist_restore(gic); in gic_runtime_resume()
46 gic_cpu_restore(gic); in gic_runtime_resume()
54 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local
57 gic_dist_save(gic); in gic_runtime_suspend()
58 gic_cpu_save(gic); in gic_runtime_suspend()
115 dev_info(dev, "GIC IRQ controller registered\n"); in gic_probe()
[all …]
H A Dirq-gic-realview.c3 * Special GIC quirks for the ARM RealView
11 #include <linux/irqchip/arm-gic.h>
58 /* The PB11MPCore GIC needs to be configured in the syscon */ in realview_gic_of_init()
69 pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); in realview_gic_of_init()
71 pr_err("RealView GIC setup: could not find syscon\n"); in realview_gic_of_init()
76 IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
77 IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmti,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
[all …]
H A Drenesas,rza1-irqc.yaml14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfsl,ls-extirq.yaml49 description: Specifies the mapping from external interrupts to GIC interrupts.
105 # in parent interrupt controller, such as GIC.
122 #include <dt-bindings/interrupt-controller/arm-gic.h>
130 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
131 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
132 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
133 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
134 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
135 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
H A Darm,gic-v5.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
34 const: arm,gic-v5
88 const: arm,gic-v5-irs
117 Present if the GIC IRS permits programming shareability and
142 const: arm,gic-v5-its
168 Present if the GIC ITS permits programming shareability and
225 compatible = "arm,gic-v5";
237 compatible = "arm,gic-v5-irs";
249 compatible = "arm,gic-v5-its";
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm53573.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/arch/mips/include/asm/
H A Dmips-gic.h8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
32 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
36 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
37 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
41 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
42 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
46 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm/mach-ux500/
H A Dpm.c11 #include <linux/irqchip/arm-gic.h>
44 /* This function decouple the gic from the prcmu */
56 /* Wait a few cycles for the gic mask completion */ in prcmu_gic_decouple()
62 /* This function recouple the gic with the prcmu */
76 * This function checks if there are pending irq on the gic. It only
77 * makes sense if the gic has been decoupled before with the
126 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
137 * This function copies the gic SPI settings to the prcmu in order to
185 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); in ux500_pm_init()
189 pr_err("could not remap GIC dist base for PM functions\n"); in ux500_pm_init()
[all …]
/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts8 #include <dt-bindings/interrupt-controller/mips-gic.h>
43 gic: interrupt-controller@1b1c0000 { label
44 compatible = "mti,gic";
51 * Declare the interrupt-parent even though the mti,gic
63 interrupt-parent = <&gic>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
241 interrupt-parent = <&gic>;
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
[all …]
H A Dmalta.dts5 #include <dt-bindings/interrupt-controller/mips-gic.h>
23 gic: interrupt-controller@1bdc0000 { label
24 compatible = "mti,gic";
31 * Declare the interrupt-parent even though the mti,gic
39 compatible = "mti,gic-timer";
50 interrupt-parent = <&gic>;
/linux/tools/testing/selftests/kvm/arm64/
H A Dvgic_init.c168 TEST_ASSERT(ret && errno == EINVAL, "GIC dist base not aligned"); in subtest_dist_rdist()
173 TEST_ASSERT(ret && errno == EINVAL, "GIC redist/cpu base not aligned"); in subtest_dist_rdist()
201 TEST_ASSERT(ret && errno == EEXIST, "GIC redist base set again"); in subtest_dist_rdist()
479 "read GICR_TYPER before GIC initialized"); in test_v3_typer_accesses()
718 * Returns 0 if it's possible to create GIC device of a given type (V2 or V3).
740 TEST_ASSERT(ret < 0 && errno == EEXIST, "create GIC device twice"); in test_kvm_device()
749 "create GIC device while other version exists"); in test_kvm_device()
824 static void test_sysreg_array(int gic, const struct sr_def *sr, int nr, in test_sysreg_array() argument
844 ret = __kvm_has_device_attr(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
849 ret = __kvm_device_attr_get(gic, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, in test_sysreg_array()
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi30 interrupt-parent = <&gic>;
84 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
85 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
86 <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
87 <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
88 <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
89 <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
90 <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
91 <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/Documentation/devicetree/bindings/pci/
H A Dhisilicon,kirin-pcie.yaml68 #include <dt-bindings/interrupt-controller/arm-gic.h>
95 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
96 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
97 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
98 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
128 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
129 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
130 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm64/boot/dts/freescale/
H A Ds32v234.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
91 gic: interrupt-controller@7d001000 { label
92 compatible = "arm,cortex-a15-gic";
108 interrupt-parent = <&gic>;
115 interrupt-parent = <&gic>;
131 interrupt-parent = <&gic>;
H A Dfsl-ls1043a.dtsi13 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
290 gic: interrupt-controller@1400000 { label
291 compatible = "arm,gic-400";
332 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
333 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
334 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
335 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
336 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
337 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/drivers/net/ethernet/microsoft/mana/
H A Dgdma_main.c787 struct gdma_irq_context *gic; in mana_gd_register_irq() local
807 gic = xa_load(&gc->irq_contexts, msi_index); in mana_gd_register_irq()
808 if (WARN_ON(!gic)) in mana_gd_register_irq()
811 spin_lock_irqsave(&gic->lock, flags); in mana_gd_register_irq()
812 list_add_rcu(&queue->entry, &gic->eq_list); in mana_gd_register_irq()
813 spin_unlock_irqrestore(&gic->lock, flags); in mana_gd_register_irq()
821 struct gdma_irq_context *gic; in mana_gd_deregister_irq() local
834 gic = xa_load(&gc->irq_contexts, msix_index); in mana_gd_deregister_irq()
835 if (WARN_ON(!gic)) in mana_gd_deregister_irq()
838 spin_lock_irqsave(&gic->lock, flags); in mana_gd_deregister_irq()
[all …]
/linux/include/linux/irqchip/
H A Darm-gic.h3 * include/linux/irqchip/arm-gic.h
143 void gic_cpu_save(struct gic_chip_data *gic);
144 void gic_cpu_restore(struct gic_chip_data *gic);
145 void gic_dist_save(struct gic_chip_data *gic);
146 void gic_dist_restore(struct gic_chip_data *gic);
155 * Initialises and registers a non-root or child GIC chip. Memory for
158 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq);

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