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/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-aemv8a.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
101 gic: interrupt-controller@2c001000 { label
102 compatible = "arm,gic-400", "arm,cortex-a15-gic";
142 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfoundation-v8.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
139 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfvp-base-revc.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
190 gic: interrupt-controller@2f000000 { label
191 compatible = "arm,gic-v3";
206 compatible = "arm,gic-v3-its";
239 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
240 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
241 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
242 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/drivers/irqchip/
H A Dirq-gic.c5 * Interrupt architecture for the GIC:
42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
114 * The GIC mapping of CPU interfaces does not necessarily match
116 * by the GIC itself.
309 pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16); in gic_set_type()
318 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
337 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
338 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
353 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
[all …]
H A Dirq-gic-pm.c9 #include <linux/irqchip/arm-gic.h>
28 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_resume() local
39 * want to restore the GIC on the very first resume. So if in gic_runtime_resume()
42 if (!gic) in gic_runtime_resume()
45 gic_dist_restore(gic); in gic_runtime_resume()
46 gic_cpu_restore(gic); in gic_runtime_resume()
54 struct gic_chip_data *gic = chip_pm->chip_data; in gic_runtime_suspend() local
57 gic_dist_save(gic); in gic_runtime_suspend()
58 gic_cpu_save(gic); in gic_runtime_suspend()
115 dev_info(dev, "GIC IRQ controller registered\n"); in gic_probe()
[all …]
H A Dirq-gic-realview.c3 * Special GIC quirks for the ARM RealView
11 #include <linux/irqchip/arm-gic.h>
58 /* The PB11MPCore GIC needs to be configured in the syscon */ in realview_gic_of_init()
69 pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n"); in realview_gic_of_init()
71 pr_err("RealView GIC setup: could not find syscon\n"); in realview_gic_of_init()
76 IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
77 IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);
H A DMakefile29 obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
30 obj-$(CONFIG_ARM_GIC_PM) += irq-gic-pm.o
31 obj-$(CONFIG_ARCH_REALVIEW) += irq-gic-realview.o
33 obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
34 obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o
35 obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v4.o irq-gic-v3-its-msi-parent.o
36 obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o
71 obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-ns.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
75 gic: interrupt-controller@21000 { label
76 compatible = "arm,cortex-a9-gic";
106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dbcm53573.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmti,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
[all …]
H A Drenesas,rza1-irqc.yaml14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Darm,gic-v3.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
[all …]
H A Dfsl,ls-extirq.yaml49 description: Specifies the mapping from external interrupts to GIC interrupts.
105 # in parent interrupt controller, such as GIC.
122 #include <dt-bindings/interrupt-controller/arm-gic.h>
130 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
131 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
132 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
133 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
134 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
135 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dvexpress-v2m-rs1.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/arch/mips/include/asm/
H A Dmips-gic.h8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
16 /* The base address of the GIC registers */
19 /* Offsets from the GIC base address to various control blocks */
31 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
32 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
36 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name) \
37 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, redir_##name)
41 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
42 CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
46 CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name) \
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
147 interrupt-parent = <&gic>;
178 interrupt-parent = <&gic>;
209 interrupt-parent = <&gic>;
311 interrupt-parent = <&gic>;
508 interrupt-parent = <&gic>;
521 interrupt-parent = <&gic>;
539 interrupt-parent = <&gic>;
581 interrupt-parent = <&gic>;
594 interrupt-parent = <&gic>;
[all …]
/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@4000080000 { label
59 compatible = "arm,gic-v3";
71 compatible = "arm,gic-v3-its";
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
120 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
121 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm/mach-ux500/
H A Dpm.c11 #include <linux/irqchip/arm-gic.h>
44 /* This function decouple the gic from the prcmu */
56 /* Wait a few cycles for the gic mask completion */ in prcmu_gic_decouple()
62 /* This function recouple the gic with the prcmu */
76 * This function checks if there are pending irq on the gic. It only
77 * makes sense if the gic has been decoupled before with the
126 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
137 * This function copies the gic SPI settings to the prcmu in order to
185 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); in ux500_pm_init()
189 pr_err("could not remap GIC dist base for PM functions\n"); in ux500_pm_init()
[all …]
/linux/arch/mips/boot/dts/mti/
H A Dsead3.dts8 #include <dt-bindings/interrupt-controller/mips-gic.h>
43 gic: interrupt-controller@1b1c0000 { label
44 compatible = "mti,gic";
51 * Declare the interrupt-parent even though the mti,gic
63 interrupt-parent = <&gic>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
241 interrupt-parent = <&gic>;
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos54xx.dtsi30 interrupt-parent = <&gic>;
84 <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
85 <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
86 <&gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
87 <&gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
88 <&gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
89 <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
90 <&gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
91 <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/linux/Documentation/devicetree/bindings/pci/
H A Dhisilicon,kirin-pcie.yaml68 #include <dt-bindings/interrupt-controller/arm-gic.h>
95 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
96 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
97 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
98 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
127 interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
128 <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
129 <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
130 <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls208xa.dtsi14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
49 gic: interrupt-controller@6000000 { label
50 compatible = "arm,gic-v3";
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
64 compatible = "arm,gic-v3-its";
298 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
299 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
300 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
301 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfsl-ls1088a.dtsi11 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
112 gic: interrupt-controller@6000000 { label
113 compatible = "arm,gic-v3";
116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
127 compatible = "arm,gic-v3-its";
257 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
258 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
259 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
260 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
[all …]

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