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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Drtsm_ve-aemv8a.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
22 interrupt-parent = <&gic>;
101 gic: interrupt-controller@2c001000 { label
102 compatible = "arm,gic-400", "arm,cortex-a15-gic";
142 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfoundation-v8.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 interrupt-parent = <&gic>;
139 interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
140 <0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
141 <0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
142 <0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dfvp-base-revc.dts13 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 interrupt-parent = <&gic>;
190 gic: interrupt-controller@2f000000 { label
191 compatible = "arm,gic-v3";
206 compatible = "arm,gic-v3-its";
239 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
240 <0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
241 <0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
242 <0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dvexpress-v2m-rs1.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Darm,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
13 ARM SMP cores are often associated with a GIC, providing per processor
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
29 - arm,arm11mp-gic
30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
34 - arm,eb11mp-gic
35 - arm,gic-400
[all …]
H A Dmips-gic.txt1 MIPS Global Interrupt Controller (GIC)
3 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
5 interrupts which can be used as IPIs. The GIC also includes a free-running
9 - compatible : Should be "mti,gic".
14 See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15 - The second cell is the GIC interrupt number.
21 - reg : Base address and length of the GIC registers. If not present,
24 to which the GIC may not route interrupts. Valid values are 2 - 7.
26 - mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
34 - compatible : Should be "mti,gic-timer".
[all …]
H A Dmti,gic.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
16 interrupts which can be used as IPIs. The GIC also includes a free-running
21 const: mti,gic
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
34 Base address and length of the GIC registers space. If not present,
42 Specifies the list of CPU interrupt vectors to which the GIC may not
55 Specifies the range of GIC interrupts that are reserved for IPIs.
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
[all …]
H A Drenesas,rza1-irqc.yaml14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
43 description: Specifies the mapping from external interrupts to GIC interrupts.
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Drenesas,rza1-irqc.txt3 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
5 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
21 - interrupt-map: Specifies the mapping from external interrupts to GIC
34 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
35 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
36 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
37 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
38 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
39 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
40 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Darm,gic-v3.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
26 - qcom,msm8996-gic-v3
27 - const: arm,gic-v3
28 - const: arm,gic-v3
73 Specifies base physical address(s) and size of the GIC
75 - GIC Distributor interface (GICD)
76 - GIC Redistributors (GICR), one range per redistributor region
77 - GIC CPU interface (GICC)
78 - GIC Hypervisor interface (GICH)
79 - GIC Virtual CPU interface (GICV)
[all …]
H A Dfsl,ls-extirq.txt21 - interrupt-map: Specifies the mapping from external interrupts to GIC
41 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
42 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
43 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
44 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
45 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
46 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
52 interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
H A Dfsl,ls-extirq.yaml49 description: Specifies the mapping from external interrupts to GIC interrupts.
105 # in parent interrupt controller, such as GIC.
122 #include <dt-bindings/interrupt-controller/arm-gic.h>
130 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
131 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
132 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
133 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
134 <4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
135 <5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm-ns.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
75 gic: interrupt-controller@21000 {
76 compatible = "arm,cortex-a9-gic";
106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
113 <0x00007000 4 &gic GIC_SP
68 gic: interrupt-controller@21000 { global() label
[all...]
H A Dbcm53573.dtsi9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 interrupt-parent = <&gic>;
41 gic: interrupt-controller@1000 { label
42 compatible = "arm,cortex-a7-gic";
82 <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
85 <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
88 <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
89 <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
90 <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <0x00002000 3 &gic GIC_SP
[all...]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2m-rs1.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
111 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
112 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
113 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
114 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
115 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
116 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
117 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
118 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
119 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dvexpress-v2m.dtsi20 #include <dt-bindings/interrupt-controller/arm-gic.h>
32 interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
33 <0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
34 <0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
35 <0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
36 <0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
37 <0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
38 <0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
39 <0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
40 <0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/sys/dts/arm/
H A Dvybrid.dtsi33 interrupt-parent = <&GIC>;
68 GIC: interrupt-controller@01c81000 { label
69 compatible = "arm,gic";
95 interrupt-parent = < &GIC >;
111 interrupt-parent = <&GIC>;
121 interrupt-parent = <&GIC>;
130 interrupt-parent = <&GIC>;
138 interrupt-parent = <&GIC>;
151 interrupt-parent = <&GIC>;
167 interrupt-parent = <&GIC>;
[all …]
H A Dzynq-7000.dtsi32 interrupt-parent = <&GIC>;
54 GIC: gic { label
55 compatible = "arm,gic";
68 interrupt-parent = <&GIC>;
76 interrupt-parent = <&GIC>;
98 interrupt-parent = <&GIC>;
107 interrupt-parent = <&GIC>;
115 interrupt-parent = <&GIC>;
137 interrupt-parent = <&GIC>;
147 interrupt-parent = <&GIC>;
[all …]
H A Dtrimslice.dts38 interrupt-parent = <&GIC>;
58 GIC: interrupt-controller@50041000 { label
59 compatible = "arm,gic";
74 interrupt-parent = < &GIC >;
81 interrupt-parent = <&GIC>;
88 interrupt-parent = <&GIC>;
100 interrupt-parent = <&GIC>;
107 interrupt-parent = <&GIC>;
115 interrupt-parent = <&GIC>;
124 interrupt-parent = <&GIC>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
142 interrupt-parent = <&gic>;
173 interrupt-parent = <&gic>;
204 interrupt-parent = <&gic>;
306 interrupt-parent = <&gic>;
408 interrupt-parent = <&gic>;
421 interrupt-parent = <&gic>;
439 interrupt-parent = <&gic>;
481 interrupt-parent = <&gic>;
494 interrupt-parent = <&gic>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/cavium/
H A Dthunder2-99xx.dtsi10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&gic>;
58 gic: interrupt-controller@4000080000 { label
59 compatible = "arm,gic-v3";
71 compatible = "arm,gic-v3-its";
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
120 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
121 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dbrcm,bus-axi.txt34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
43 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
44 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
45 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
/freebsd/sys/dev/mana/
H A Dgdma_main.c633 struct gdma_irq_context *gic; in mana_gd_register_irq() local
665 gic = &gc->irq_contexts[msi_index]; in mana_gd_register_irq()
667 if (unlikely(gic->handler || gic->arg)) { in mana_gd_register_irq()
673 gic->arg = queue; in mana_gd_register_irq()
675 gic->handler = mana_gd_process_eq_events; in mana_gd_register_irq()
678 msi_index, gic->msix_e.vector, rman_get_start(gic->res)); in mana_gd_register_irq()
687 struct gdma_irq_context *gic; in mana_gd_deregiser_irq() local
700 gic = &gc->irq_contexts[msix_index]; in mana_gd_deregiser_irq()
701 gic->handler = NULL; in mana_gd_deregiser_irq()
702 gic->arg = NULL; in mana_gd_deregiser_irq()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/apm/
H A Dapm-shadowcat.dtsi10 interrupt-parent = <&gic>;
120 gic: interrupt-controller@78090000 { label
121 compatible = "arm,cortex-a15-gic";
126 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
128 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
129 <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
130 <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
131 <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
133 compatible = "arm,gic-v2m-frame";
138 compatible = "arm,gic-v2m-frame";
[all …]
/freebsd/sys/contrib/device-tree/src/mips/mti/
H A Dsead3.dts8 #include <dt-bindings/interrupt-controller/mips-gic.h>
43 gic: interrupt-controller@1b1c0000 { label
44 compatible = "mti,gic";
51 * Declare the interrupt-parent even though the mti,gic
63 interrupt-parent = <&gic>;
64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
226 interrupt-parent = <&gic>;
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
241 interrupt-parent = <&gic>;
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
[all …]

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