Searched +full:gic +full:- +full:v5 +full:- +full:iwb (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB)10 - Lorenzo Pieralisi <lpieralisi@kernel.org>11 - Marc Zyngier <maz@kernel.org>20 GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible24 - $ref: /schemas/interrupt-controller.yaml#28 const: arm,gic-v5-iwb[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright (C) 2024-2025 ARM Limited, All Rights Reserved.5 #define pr_fmt(fmt) "GICv5 IWB: " fmt15 #include <linux/irqchip/arm-gic-v5.h>24 return readl_relaxed(iwb_node->iwb_base + reg_offset); in iwb_readl_relaxed()30 writel_relaxed(val, iwb_node->iwb_base + reg_offset); in iwb_writel_relaxed()35 return gicv5_wait_for_op_atomic(iwb_node->iwb_base, GICV5_IWB_WENABLE_STATUSR, in gicv5_iwb_wait_for_wenabler()46 if (n >= iwb_node->nr_regs) { in __gicv5_iwb_set_wire_enable()48 return -EINVAL; in __gicv5_iwb_set_wire_enable()52 * Enable IWB wire/pin at this point in __gicv5_iwb_set_wire_enable()[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_IRQCHIP) += irqchip.o4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o11 obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o[all …]