Lines Matching +full:gic +full:- +full:v5 +full:- +full:iwb
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5-iwb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller, version 5 Interrupt Wire Bridge (IWB)
10 - Lorenzo Pieralisi <lpieralisi@kernel.org>
11 - Marc Zyngier <maz@kernel.org>
20 GICv5 has zero or more Interrupt Wire Bridges (IWB) that are responsible
24 - $ref: /schemas/interrupt-controller.yaml#
28 const: arm,gic-v5-iwb
32 - description: IWB control frame
34 "#address-cells":
37 "#interrupt-cells":
39 The 1st cell corresponds to the IWB wire.
44 1 = low-to-high edge triggered
45 2 = high-to-low edge triggered
46 4 = active high level-sensitive
47 8 = active low level-sensitive
51 interrupt-controller: true
53 msi-parent:
57 - compatible
58 - reg
59 - "#interrupt-cells"
60 - interrupt-controller
61 - msi-parent
66 - |
67 interrupt-controller@2f000000 {
68 compatible = "arm,gic-v5-iwb";
71 #address-cells = <0>;
73 #interrupt-cells = <2>;
74 interrupt-controller;
76 msi-parent = <&its0 64>;