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/linux/Documentation/devicetree/bindings/i2c/
H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
19 controller is only compatible with "nvidia,tegra20-i2c".
20 const: nvidia,tegra20-i2c
[all …]
/linux/Documentation/devicetree/bindings/serial/
H A Drenesas,scif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - items:
16 - enum:
17 - renesas,scif-r7s72100 # RZ/A1H
18 - const: renesas,scif # generic SCIF compatible UART
20 - items:
21 - enum:
[all …]
H A Drenesas,hscif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,hscif-r8a7778 # R-Car M1
21 - renesas,hscif-r8a7779 # R-Car H1
22 - const: renesas,rcar-gen1-hscif # R-Car Gen1
[all …]
H A Drenesas,em-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Magnus Damm <magnus.damm@gmail.com>
15 - items:
16 - enum:
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
20 - items:
[all …]
H A Drenesas,sci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,r9a07g043-sci # RZ/G2UL and RZ/Five
21 - renesas,r9a07g044-sci # RZ/G2{L,LC}
22 - renesas,r9a07g054-sci # RZ/V2L
[all …]
H A Drenesas,scifa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,scifa-r8a73a4 # R-Mobile APE6
21 - renesas,scifa-r8a7740 # R-Mobile A1
22 - renesas,scifa-sh73a0 # SH-Mobile AG5
[all …]
H A Drenesas,scifb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,scifb-r8a73a4 # R-Mobile APE6
21 - renesas,scifb-r8a7740 # R-Mobile A1
22 - renesas,scifb-sh73a0 # SH-Mobile AG5
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dnixge.txt4 - compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
5 older device trees with DMA engines co-located in the address map,
7 - reg: Address and length of the register set for the device. It contains the
8 information of registers in the same order as described by reg-names.
9 - reg-names: Should contain the reg names
12 - interrupts: Should contain tx and rx interrupt
13 - interrupt-names: Should be "rx" and "tx"
14 - phy-mode: See ethernet.txt file in the same directory.
15 - nvmem-cells: Phandle of nvmem cell containing the MAC address
16 - nvmem-cell-names: Should be "address"
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/linux/arch/mips/boot/dts/brcm/
H A Dbcm7346.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
H A Dbcm7425.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <163125000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
H A Dbcm7435.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <175625000>;
42 cpu_intc: interrupt-controller {
43 #address-cells = <0>;
44 compatible = "mti,cpu-interrupt-controller";
46 interrupt-controller;
[all …]
H A Dbcm7420.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #address-cells = <1>;
4 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 mips-hpt-frequency = <93750000>;
30 cpu_intc: interrupt-controller {
31 #address-cells = <0>;
32 compatible = "mti,cpu-interrupt-controller";
34 interrupt-controller;
[all …]
/linux/Documentation/driver-api/
H A Dgeneric_pt.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Generic Radix Page Table
7 .. kernel-doc:: include/linux/generic_pt/common.h
8 :doc: Generic Radix Page Table
10 .. kernel-doc:: drivers/iommu/generic_pt/pt_defs.h
11 :doc: Generic Page Table Language
16 Generic PT is structured as a multi-compilation system. Since each format
17 provides an API using a common set of names there can be only one format active
22 map/unmap, etc.) and the per-format code can be directly inlined into the
23 per-format compilation unit. For something like IOMMU each format will be
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,lan966x-gck.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/microchip,lan966x-gck.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN966X Generic Clock Controller
10 - Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
13 The LAN966X Generic clock controller contains 3 PLLs - cpu_clk,
20 - enum:
21 - microchip,lan966x-gck
22 - microchip,lan9691-gck
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-mcbin.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
14 compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
15 "marvell,armada-ap806-quad", "marvell,armada-ap806";
18 stdout-path = "serial0:115200n8";
34 v_3_3: regulator-3-3v {
35 compatible = "regulator-fixed";
36 regulator-name = "v_3_3";
37 regulator-min-microvolt = <3300000>;
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-h3-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun6i-rtc.h>
44 #include <dt-bindings/clock/sun8i-de2.h>
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 interrupt-parent = <&gic>;
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dgeneric-adc-thermal.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/thermal/generic-adc-thermal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Laxman Dewangan <ldewangan@nvidia.com>
16 temperature using voltage-temperature lookup table.
18 $ref: thermal-sensor.yaml#
22 const: generic-adc-thermal
24 '#thermal-sensor-cells':
27 io-channels:
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dspi-ath79.txt4 - compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
5 - reg: Base address and size of the controllers memory area
6 - clocks: phandle of the AHB clock.
7 - clock-names: has to be "ahb".
8 - #address-cells: <1>, as required by generic SPI binding.
9 - #size-cells: <0>, also as required by generic SPI binding.
11 Child nodes as per the generic SPI binding.
16 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
20 clock-names = "ahb";
22 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h616.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h616-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/clock/sun6i-rtc.h>
10 #include <dt-bindings/reset/sun50i-h616-ccu.h>
11 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl-bindings.txt4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
15 need to reconfigure pins at run-time, for example to tri-state pins when the
17 states. The number and names of those states is defined by the client device's
21 for client device device tree nodes to map those state names to the pin
38 assigned a name. When names are used, another property exists to map from
39 those names to the integer IDs.
43 IDs that must be provided, or whether to define the set of state names that
47 pinctrl-0: List of phandles, each pointing at a pin configuration
65 pinctrl-1: List of phandles, each pointing at a pin configuration
68 pinctrl-n: List of phandles, each pointing at a pin configuration
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
29 Generic AHCI registers space conforming to the Serial ATA AHCI
[all …]
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
20 #phy-cells = <1>;
25 compatible = "generic-xhci";
[all …]
/linux/arch/arc/boot/dts/
H A Dvdk_axs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
10 compatible = "simple-bus";
11 #address-cells = <1>;
12 #size-cells = <1>;
14 interrupt-parent = <&mb_intc>;
18 compatible = "fixed-clock";
19 clock-frequency = <50000000>;
20 #clock-cells = <0>;
24 compatible = "fixed-clock";
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr7s9210.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r7s9210-cpg-mssr.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <1>;
16 #size-cells = <1>;
20 #clock-cells = <0>;
21 compatible = "fixed-clock";
23 clock-frequency = <0>;
27 #clock-cells = <0>;
[all …]

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