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/linux/Documentation/devicetree/bindings/ata/
H A Dcortina,gemini-sata-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini SATA Bridge
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
28 reset-names:
30 - const: sata0
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/linux/drivers/ata/
H A Dsata_gemini.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cortina Systems Gemini SATA bridge add-on to Faraday FTIDE010
24 * struct sata_gemini - a state container for a Gemini SATA bridge
28 * @ide_pins: if the device is using the plain IDE interface pins
50 * Values of IDE IOMUX bits in the misc control register
52 * Bits 26:24 are "IDE IO Select", which decides what SATA
53 * adapters are connected to which of the two IDE/ATA
54 * controllers in the Gemini. We can connect the two IDE blocks
55 * to one SATA adapter each, both acting as master, or one IDE
56 * blocks to two SATA adapters so the IDE block can act in a
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/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for Cortina systems Gemini SoC
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
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H A Dgemini-nas4220b.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the Gemini-based Raidsonic NAS IB-4220-B
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
12 model = "Raidsonic NAS IB-4220-B";
13 compatible = "raidsonic,ib-4220-b", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
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H A Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
4 * Gemini reference design, also initially called
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
11 #include "gemini.dtsi"
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
16 compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini";
17 #address-cells = <1>;
18 #size-cells = <1>;
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H A Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
7 #include "gemini.dtsi"
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
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H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
13 compatible = "itian,sq201", "cortina,gemini";
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
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H A Dgemini-dlink-dns-313.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
6 /dts-v1/;
8 #include "gemini.dtsi"
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
14 compatible = "dlink,dns-313", "cortina,gemini";
15 #address-cells = <1>;
16 #size-cells = <1>;
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/linux/drivers/pinctrl/
H A Dpinctrl-gemini.c2 * Driver for the Gemini pin controller
6 * This is a group-only pin controller.
19 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-utils.h"
26 #define DRIVER_NAME "pinctrl-gemini"
29 * struct gemini_pin_conf - information about configuring a pin
41 * struct gemini_pmx - state holder for the gemini pin controller
47 * @flash_pin: whether the flash pin (extended pins for parallel
64 * struct gemini_pin_group - describes a Gemini pin group
66 * @pins: an array of discrete physical pins used in this group, taken
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